| /* |
| * tlv320aic32x4.h |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| |
| #ifndef _TLV320AIC32X4_H |
| #define _TLV320AIC32X4_H |
| |
| struct device; |
| struct regmap_config; |
| |
| extern const struct regmap_config aic32x4_regmap_config; |
| int aic32x4_probe(struct device *dev, struct regmap *regmap); |
| int aic32x4_remove(struct device *dev); |
| |
| /* tlv320aic32x4 register space (in decimal to match datasheet) */ |
| |
| #define AIC32X4_PAGE1 128 |
| |
| #define AIC32X4_PSEL 0 |
| #define AIC32X4_RESET 1 |
| #define AIC32X4_CLKMUX 4 |
| #define AIC32X4_PLLPR 5 |
| #define AIC32X4_PLLJ 6 |
| #define AIC32X4_PLLDMSB 7 |
| #define AIC32X4_PLLDLSB 8 |
| #define AIC32X4_NDAC 11 |
| #define AIC32X4_MDAC 12 |
| #define AIC32X4_DOSRMSB 13 |
| #define AIC32X4_DOSRLSB 14 |
| #define AIC32X4_NADC 18 |
| #define AIC32X4_MADC 19 |
| #define AIC32X4_AOSR 20 |
| #define AIC32X4_CLKMUX2 25 |
| #define AIC32X4_CLKOUTM 26 |
| #define AIC32X4_IFACE1 27 |
| #define AIC32X4_IFACE2 28 |
| #define AIC32X4_IFACE3 29 |
| #define AIC32X4_BCLKN 30 |
| #define AIC32X4_IFACE4 31 |
| #define AIC32X4_IFACE5 32 |
| #define AIC32X4_IFACE6 33 |
| #define AIC32X4_GPIOCTL 52 |
| #define AIC32X4_DOUTCTL 53 |
| #define AIC32X4_DINCTL 54 |
| #define AIC32X4_MISOCTL 55 |
| #define AIC32X4_SCLKCTL 56 |
| #define AIC32X4_DACSPB 60 |
| #define AIC32X4_ADCSPB 61 |
| #define AIC32X4_DACSETUP 63 |
| #define AIC32X4_DACMUTE 64 |
| #define AIC32X4_LDACVOL 65 |
| #define AIC32X4_RDACVOL 66 |
| #define AIC32X4_ADCSETUP 81 |
| #define AIC32X4_ADCFGA 82 |
| #define AIC32X4_LADCVOL 83 |
| #define AIC32X4_RADCVOL 84 |
| #define AIC32X4_LAGC1 86 |
| #define AIC32X4_LAGC2 87 |
| #define AIC32X4_LAGC3 88 |
| #define AIC32X4_LAGC4 89 |
| #define AIC32X4_LAGC5 90 |
| #define AIC32X4_LAGC6 91 |
| #define AIC32X4_LAGC7 92 |
| #define AIC32X4_RAGC1 94 |
| #define AIC32X4_RAGC2 95 |
| #define AIC32X4_RAGC3 96 |
| #define AIC32X4_RAGC4 97 |
| #define AIC32X4_RAGC5 98 |
| #define AIC32X4_RAGC6 99 |
| #define AIC32X4_RAGC7 100 |
| #define AIC32X4_PWRCFG (AIC32X4_PAGE1 + 1) |
| #define AIC32X4_LDOCTL (AIC32X4_PAGE1 + 2) |
| #define AIC32X4_OUTPWRCTL (AIC32X4_PAGE1 + 9) |
| #define AIC32X4_CMMODE (AIC32X4_PAGE1 + 10) |
| #define AIC32X4_HPLROUTE (AIC32X4_PAGE1 + 12) |
| #define AIC32X4_HPRROUTE (AIC32X4_PAGE1 + 13) |
| #define AIC32X4_LOLROUTE (AIC32X4_PAGE1 + 14) |
| #define AIC32X4_LORROUTE (AIC32X4_PAGE1 + 15) |
| #define AIC32X4_HPLGAIN (AIC32X4_PAGE1 + 16) |
| #define AIC32X4_HPRGAIN (AIC32X4_PAGE1 + 17) |
| #define AIC32X4_LOLGAIN (AIC32X4_PAGE1 + 18) |
| #define AIC32X4_LORGAIN (AIC32X4_PAGE1 + 19) |
| #define AIC32X4_HEADSTART (AIC32X4_PAGE1 + 20) |
| #define AIC32X4_MICBIAS (AIC32X4_PAGE1 + 51) |
| #define AIC32X4_LMICPGAPIN (AIC32X4_PAGE1 + 52) |
| #define AIC32X4_LMICPGANIN (AIC32X4_PAGE1 + 54) |
| #define AIC32X4_RMICPGAPIN (AIC32X4_PAGE1 + 55) |
| #define AIC32X4_RMICPGANIN (AIC32X4_PAGE1 + 57) |
| #define AIC32X4_FLOATINGINPUT (AIC32X4_PAGE1 + 58) |
| #define AIC32X4_LMICPGAVOL (AIC32X4_PAGE1 + 59) |
| #define AIC32X4_RMICPGAVOL (AIC32X4_PAGE1 + 60) |
| |
| #define AIC32X4_FREQ_12000000 12000000 |
| #define AIC32X4_FREQ_24000000 24000000 |
| #define AIC32X4_FREQ_25000000 25000000 |
| |
| /* Bits, masks, and shifts */ |
| |
| /* AIC32X4_CLKMUX */ |
| #define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2) |
| #define AIC32X4_PLL_CLKIN_SHIFT (2) |
| #define AIC32X4_PLL_CLKIN_MCLK (0x00) |
| #define AIC32X4_PLL_CLKIN_BCKL (0x01) |
| #define AIC32X4_PLL_CLKIN_GPIO1 (0x02) |
| #define AIC32X4_PLL_CLKIN_DIN (0x03) |
| #define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0) |
| #define AIC32X4_CODEC_CLKIN_SHIFT (0) |
| #define AIC32X4_CODEC_CLKIN_MCLK (0x00) |
| #define AIC32X4_CODEC_CLKIN_BCLK (0x01) |
| #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02) |
| #define AIC32X4_CODEC_CLKIN_PLL (0x03) |
| |
| /* AIC32X4_PLLPR */ |
| #define AIC32X4_PLLEN BIT(7) |
| #define AIC32X4_PLL_P_MASK GENMASK(6, 4) |
| #define AIC32X4_PLL_P_SHIFT (4) |
| #define AIC32X4_PLL_R_MASK GENMASK(3, 0) |
| |
| /* AIC32X4_NDAC */ |
| #define AIC32X4_NDACEN BIT(7) |
| #define AIC32X4_NDAC_MASK GENMASK(6, 0) |
| |
| /* AIC32X4_MDAC */ |
| #define AIC32X4_MDACEN BIT(7) |
| #define AIC32X4_MDAC_MASK GENMASK(6, 0) |
| |
| /* AIC32X4_NADC */ |
| #define AIC32X4_NADCEN BIT(7) |
| #define AIC32X4_NADC_MASK GENMASK(6, 0) |
| |
| /* AIC32X4_MADC */ |
| #define AIC32X4_MADCEN BIT(7) |
| #define AIC32X4_MADC_MASK GENMASK(6, 0) |
| |
| /* AIC32X4_BCLKN */ |
| #define AIC32X4_BCLKEN BIT(7) |
| #define AIC32X4_BCLK_MASK GENMASK(6, 0) |
| |
| /* AIC32X4_IFACE1 */ |
| #define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6) |
| #define AIC32X4_IFACE1_DATATYPE_SHIFT (6) |
| #define AIC32X4_I2S_MODE (0x00) |
| #define AIC32X4_DSP_MODE (0x01) |
| #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02) |
| #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03) |
| #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4) |
| #define AIC32X4_IFACE1_DATALEN_SHIFT (4) |
| #define AIC32X4_WORD_LEN_16BITS (0x00) |
| #define AIC32X4_WORD_LEN_20BITS (0x01) |
| #define AIC32X4_WORD_LEN_24BITS (0x02) |
| #define AIC32X4_WORD_LEN_32BITS (0x03) |
| #define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2) |
| #define AIC32X4_BCLKMASTER BIT(2) |
| #define AIC32X4_WCLKMASTER BIT(3) |
| |
| /* AIC32X4_IFACE2 */ |
| #define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0) |
| |
| /* AIC32X4_IFACE3 */ |
| #define AIC32X4_BCLKINV_MASK BIT(3) |
| #define AIC32X4_BDIVCLK_MASK GENMASK(1, 0) |
| #define AIC32X4_BDIVCLK_SHIFT (0) |
| #define AIC32X4_DAC2BCLK (0x00) |
| #define AIC32X4_DACMOD2BCLK (0x01) |
| #define AIC32X4_ADC2BCLK (0x02) |
| #define AIC32X4_ADCMOD2BCLK (0x03) |
| |
| /* AIC32X4_DACSETUP */ |
| #define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2) |
| #define AIC32X4_LDAC2RCHN BIT(5) |
| #define AIC32X4_LDAC2LCHN BIT(4) |
| #define AIC32X4_RDAC2LCHN BIT(3) |
| #define AIC32X4_RDAC2RCHN BIT(2) |
| |
| /* AIC32X4_DACMUTE */ |
| #define AIC32X4_MUTEON 0x0C |
| |
| /* AIC32X4_ADCSETUP */ |
| #define AIC32X4_LADC_EN BIT(7) |
| #define AIC32X4_RADC_EN BIT(6) |
| |
| /* AIC32X4_PWRCFG */ |
| #define AIC32X4_AVDDWEAKDISABLE BIT(3) |
| |
| /* AIC32X4_LDOCTL */ |
| #define AIC32X4_LDOCTLEN BIT(0) |
| |
| /* AIC32X4_CMMODE */ |
| #define AIC32X4_LDOIN_18_36 BIT(0) |
| #define AIC32X4_LDOIN2HP BIT(1) |
| |
| /* AIC32X4_MICBIAS */ |
| #define AIC32X4_MICBIAS_LDOIN BIT(3) |
| #define AIC32X4_MICBIAS_2075V 0x60 |
| |
| /* AIC32X4_LMICPGANIN */ |
| #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 |
| #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 |
| |
| /* AIC32X4_RMICPGANIN */ |
| #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 |
| #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 |
| |
| #endif /* _TLV320AIC32X4_H */ |
