arm: tegra3: Fix bootup up issue
At bootup time device enters in standby state as
CLK_RST_CONTROLLER_SCLK_BURST_POLICY is not set correctly.
This change correctly sets clock burst policy.
BUG = None
TEST= Build OK for Seaboard,Cardhu and Waluigi.
Tested on Cardhu and waluigi. Device boots up.
Change-Id: I598ca7bcfc4a39ecaa68c211d3439ac3569c6e44
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/24164
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Tested-by: Tom Warren <twarren@nvidia.com>
Commit-Ready: Tom Warren <twarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
index 02772d4..5281e8f 100644
--- a/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
+++ b/arch/arm/cpu/armv7/tegra3/warmboot_avp.c
@@ -81,7 +81,7 @@
reg = SCLK_SWAKE_FIQ_SRC_CLKM | SCLK_SWAKE_IRQ_SRC_CLKM |
SCLK_SWAKE_RUN_SRC_CLKM | SCLK_SWAKE_IDLE_SRC_CLKM |
- SCLK_SYS_STATE_RUN;
+ (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
writel(reg, &clkrst->crc_sclk_brst_pol);
/* Update PLLP output dividers for 408 MHz operation */
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 6bf9cb6..d170b3c 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -275,7 +275,6 @@
#define SUPER_CDIV_ENB (1 << 31)
/* CRC_SCLK_BURST_POLICY_0 28h */
-#define SCLK_SYS_STATE_RUN (2 << 28)
#define SCLK_SWAKE_FIQ_SRC_CLKM (0 << 12)
#define SCLK_SWAKE_IRQ_SRC_CLKM (0 << 8)
#define SCLK_SWAKE_RUN_SRC_CLKM (0 << 4)
