UPSTREAM: riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with
featurei suffixd charactersa, it also comes with feature_ful suffix_ed
words_mith. Much creative, very appreciate.
To accommodate for this madness, enable the already existing (but off by
default) support for that in our gcc11 build, support using by detecting
the compiler's behavior in xcompile and pass that knowledge along to our
build system.
Then cross our fingers and hope for the best!
(cherry picked from commit 92e06f08d949498de1489c3570c6b387bbc249fb)
Original-Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd
Original-Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
CopyBot-Skipped-File: util/crossgcc/buildgcc
GitOrigin-RevId: f0d5f67e46cac62f485805626ca4a7c4dd622a08
Change-Id: I3c5bb55980b9d6d2729dd1ec9ce76e04007e9a03
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3903327
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 272768d..bbbdeb0 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -21,19 +21,25 @@
endif
endif
+# Needed for -print-libgcc-file-name which gets confused about all those arch
+# suffixes in ARCH_SUFFIX_riscv.
+simple_riscv_flags = $(riscv_flags)
+
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
-riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
+riscv_flags += -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
+simple_riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
else
riscv_flags += $(_rv_flags)
+simple_riscv_flags += $(_rv_flags)
endif
-riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
+riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH)$(ARCH_SUFFIX_riscv) -mabi=$(CONFIG_RISCV_ABI)
-COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name)
+COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(simple_riscv_flags) -print-libgcc-file-name)
-COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)
+COMPILER_RT_romstage = $(shell $(GCC_romstage) $(simple_riscv_flags) -print-libgcc-file-name)
-COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)
+COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(simple_riscv_flags) -print-libgcc-file-name)
################################################################################
## bootblock
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index e13996f..e35904f 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -202,6 +202,10 @@
"$LDFLAGS --fix-cortex-a53-843419" && \
LDFLAGS_ARM64_A53_ERRATUM_843419+=" --fix-cortex-a53-843419"
;;
+ riscv)
+ testcc "$GCC" "$FLAGS_GCC -march=rv64iadc_zicsr_zifencei" &&
+ ARCH_SUFFIX="_zicsr_zifencei"
+ ;;
esac
}
@@ -221,6 +225,7 @@
# elf${TWIDTH}-${TBFDARCH} toolchain (${GCC})
ARCH_SUPPORTED+=${TARCH}
SUBARCH_SUPPORTED+=${TSUPP-${TARCH}}
+ARCH_SUFFIX_${TARCH}:=${ARCH_SUFFIX}
# GCC
GCC_CC_${TARCH}:=${GCC}
@@ -399,6 +404,7 @@
unset TABI TARCH TBFDARCH TCLIST TENDIAN TSUPP TWIDTH
unset CC_RT_EXTRA_GCC CC_RT_EXTRA_CLANG
unset GCC CLANG
+ unset ARCH_SUFFIX
if type "arch_config_$architecture" > /dev/null; then
"arch_config_$architecture"
else
