| commit | 0654a747eb52c5861a6ef421e421b0a465d39e44 | [log] [tgz] |
|---|---|---|
| author | CopyBot <copybot.service@gmail.com> | Mon Sep 19 10:38:12 2022 +0000 |
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Mon Sep 19 13:09:31 2022 +0000 |
| tree | 9d6433bc767755a9cf1ad0db5855e34ea7740e26 | |
| parent | 7030287db94ceff290f581f56d67fadd95a2d13e [diff] |
UPSTREAM: riscv: Enable the newfangled way of selecting instruction sets gcc12+ will require riscv architecture selection to come not only with featurei suffixd charactersa, it also comes with feature_ful suffix_ed words_mith. Much creative, very appreciate. To accommodate for this madness, enable the already existing (but off by default) support for that in our gcc11 build, support using by detecting the compiler's behavior in xcompile and pass that knowledge along to our build system. Then cross our fingers and hope for the best! (cherry picked from commit 92e06f08d949498de1489c3570c6b387bbc249fb) Original-Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd Original-Signed-off-by: Patrick Georgi <patrick@coreboot.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Elyes Haouas <ehaouas@noos.fr> CopyBot-Skipped-File: util/crossgcc/buildgcc GitOrigin-RevId: f0d5f67e46cac62f485805626ca4a7c4dd622a08 Change-Id: I3c5bb55980b9d6d2729dd1ec9ce76e04007e9a03 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3903327 Tested-by: CopyBot Service Account <copybot.service@gmail.com> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.