UPSTREAM: mb/google/volteer: Fix eldrid DPTF's passive and critical policies
Because the entries were formatted differently to the baseboard, the
devicetree overrides didn't work as intended, and all 5 entries from
the baseboard were included, and then the overrides were applied, but
the baseboard's entries were kept, so there were duplicate ACPI
entries, which causes errors when parsing the table.
Fixes: 5f30ae3714d ("mb/google/volteer: update thermal table for Eldrid")
BUG=b:181034399
TEST=compile, verify static.c is correct now
Change-Id: I29c185c98ce857038bd0bcfada13bfa2470abe0b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Original-Commit-Id: 74dfbd09feea216da5a91f6768038de8cf37d8aa
Original-Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Original-Change-Id: I32fe2eae591ed4d3c08378977c463327f7ee1100
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/51044
Original-Reviewed-by: YH Lin <yueherngl@google.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2720016
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
index 617ce8a..6d50fac 100644
--- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
@@ -99,12 +99,14 @@
register "policies.active" = "{[0] = {.target=DPTF_NONE}}"
## Passive Policy
- register "policies.passive[0]" = "DPTF_PASSIVE(CPU,CPU,87,5000)"
- register "policies.passive[1]" = "DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60.8,6000)"
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU,CPU,87,5000),
+ [1] = DPTF_PASSIVE(CPU,TEMP_SENSOR_2,60.8,6000)}"
## Critical Policy
- register "policies.critical[0]" = "DPTF_CRITICAL(CPU,100,SHUTDOWN)"
- register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_2,75,SHUTDOWN)"
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU,100,SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_2,75,SHUTDOWN)}"
## Power Limits Control
# 3-15W PL1 in 200mW increments, avg over 26-34s interval
