commit | fc1ec8562ae3db4630008eff84bdc5840a4a3a2b | [log] [tgz] |
---|---|---|
author | John Zhao <john.zhao@intel.com> | Tue Feb 16 09:22:47 2021 -0800 |
committer | Commit Bot <commit-bot@chromium.org> | Tue Feb 23 22:31:02 2021 +0000 |
tree | 3128fb58d74bfb1bb752ef36370a380a0fbb06ff | |
parent | e211bc6bbd4f3b5bd81605c00ba98c763018dea5 [diff] |
UPSTREAM: soc/intel/tigerlake: Remove polling for Link Active Status at resume Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not applicable for SW CM platform at the resume sequence. This change removes the pollng for "LA == 1" to improve resume performance. BUG=b:177519081 TEST=Boot to kernel and validated s0ix on Voxel board. Change-Id: I2b461bdc093f9900adcfa92041050dbc8befeeff Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Original-Commit-Id: 2c7842407af8e84b28d41e8369ccf199748f65ce Original-Signed-off-by: John Zhao <john.zhao@intel.com> Original-Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2716762
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.