Revert "UPSTREAM: mb/google/fizz: Enable I2C bus 2"
This reverts commit dc25bdb67058b0fa36a31aa2afb10e26f7e930bb.
Reason for revert: Reverting for b/78220865.
Original change's description:
> UPSTREAM: mb/google/fizz: Enable I2C bus 2
>
> I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase
> it was idle.
>
> Google CFM add-in card is going to use this I2C bus so it needs to be
> re-enabled.
>
> BUG=b:73006317
> TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is
> working properly.
>
> Change-Id: I49ed171c26bfc8057de4ae5c56c7497c1837072b
> Signed-off-by: Martin Roth <martinroth@chromium.org>
> Original-Commit-Id: 1fa724b40c752704c0b9c54439a2d773af354088
> Original-Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808
> Original-Signed-off-by: Zhongze Hu <frankhu@chromium.org>
> Original-Reviewed-on: https://review.coreboot.org/25258
> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
> Original-Reviewed-by: Shelley Chen <shchen@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/973908
> (cherry picked from commit 4f7ddd9a0fac3f272aab5740c5e17d0bb0cae694)
> Reviewed-on: https://chromium-review.googlesource.com/975926
> Reviewed-by: Zhongze Hu <frankhu@google.com>
> Commit-Queue: Zhongze Hu <frankhu@google.com>
> Tested-by: Zhongze Hu <frankhu@google.com>
Bug: b:73006317
Change-Id: I96aa6e46b09c44a0f4659a2807a10d803d046e7d
Reviewed-on: https://chromium-review.googlesource.com/1026092
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index ec763d6..5eeb03c 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -296,9 +296,9 @@
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
- [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
- [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
@@ -329,9 +329,9 @@
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Thermal Subsystem
- device pci 15.0 on end # I2C #0
+ device pci 15.0 off end # I2C #0
device pci 15.1 off end # I2C #1
- device pci 15.2 on end # I2C #2
+ device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
