commit 6de890f6bc707c96228c66bc5d25cf99ce2dfeb2
author Aamir Bohra <aamir.bohra@intel.com> Thu May 25 14:38:37 2017 +0530
committer chrome-bot <chrome-bot@chromium.org> Mon Jun 05 18:33:55 2017 -0700
tree 67849ee27387ecc0341bd45630e132b267569874
parent 351df744311894d28a1da33122968f5dfca121e9

UPSTREAM: soc/intel/apollolake: Use Intel timer common code

BUG=none
BRANCH=none
TEST=none

Change-Id: If18005866011f1103bf9d95376a9ffdde035139f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c9cf304c7a4512bef50d266c21d7a5adeebe74a
Original-Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19913
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/524604

src/soc/intel/apollolake/Kconfig

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index fe72c07..b0fd4b1 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -62,6 +62,7 @@
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_SA
+	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XDCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI

src/soc/intel/apollolake/tsc_freq.c

diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
index 885311c..18d28d8 100644
--- a/src/soc/intel/apollolake/tsc_freq.c
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -23,12 +23,6 @@
 #include <delay.h>
 #include "chip.h"
 
-unsigned long tsc_freq_mhz(void)
-{
-	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
-	return (CONFIG_CPU_BCLK_MHZ * ((msr.lo >> 8) & 0xff));
-}
-
 void set_max_freq(void)
 {
 	msr_t msr, msr_rd;