commit | 482baf16d0e146784940d3a259baef5465dc2c1e | [log] [tgz] |
---|---|---|
author | Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> | Fri Jan 24 12:45:13 2020 -0700 |
committer | Commit Bot <commit-bot@chromium.org> | Wed Jan 29 18:12:42 2020 +0000 |
tree | fc26d4c765a0a8d1d162e70c712fcdc50a417615 | |
parent | 5b56ff0b45bf15c66d3ad878bf8417f568a7e124 [diff] |
HACK!!! Disable stage cache The trembyle-bringup branch still contains a patch placing TSEG in cbmem. The stage_cache feature stuffs a copy of ramstage in TSEG for safe-keeping so that resume has access to a ramstage in RAM vs. pulling pulling it from flash again. Unfortunately the stage_cache init is hooked simultaneously with allocating TSEG in cbmem and we can't control the ordering. Therefore these two ideas are inherently incompatible with each other. Hack it out here for S3 entry expediency. Upstream will have a more architecturally pure implementation. Change-Id: Id798aa56372c149579f364345077fe8726c493dd Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2020370 Commit-Queue: Eric Peers <epeers@google.com> Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.