tree fc26d4c765a0a8d1d162e70c712fcdc50a417615
parent 5b56ff0b45bf15c66d3ad878bf8417f568a7e124
author Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> 1579895113 -0700
committer Commit Bot <commit-bot@chromium.org> 1580321562 +0000

HACK!!! Disable stage cache

The trembyle-bringup branch still contains a patch placing TSEG in
cbmem.  The stage_cache feature stuffs a copy of ramstage in TSEG
for safe-keeping so that resume has access to a ramstage in RAM vs.
pulling pulling it from flash again.

Unfortunately the stage_cache init is hooked simultaneously with
allocating TSEG in cbmem and we can't control the ordering.
Therefore these two ideas are inherently incompatible with each
other.  Hack it out here for S3 entry expediency.  Upstream will
have a more architecturally pure implementation.

Change-Id: Id798aa56372c149579f364345077fe8726c493dd
Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2020370
Commit-Queue: Eric Peers <epeers@google.com>
Tested-by: Eric Peers <epeers@google.com>
Reviewed-by: Eric Peers <epeers@google.com>