HACK!!! Disable stage cache
The trembyle-bringup branch still contains a patch placing TSEG in
cbmem. The stage_cache feature stuffs a copy of ramstage in TSEG
for safe-keeping so that resume has access to a ramstage in RAM vs.
pulling pulling it from flash again.
Unfortunately the stage_cache init is hooked simultaneously with
allocating TSEG in cbmem and we can't control the ordering.
Therefore these two ideas are inherently incompatible with each
other. Hack it out here for S3 entry expediency. Upstream will
have a more architecturally pure implementation.
Change-Id: Id798aa56372c149579f364345077fe8726c493dd
Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2020370
Commit-Queue: Eric Peers <epeers@google.com>
Tested-by: Eric Peers <epeers@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 7d82099..84bf286 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -63,6 +63,7 @@
select UDK_2017_BINDING
select HAVE_CF9_RESET
select HAVE_ESPI_INIT_DEBUG
+ select NO_STAGE_CACHE
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
