commit 2d0cd2190b1f394dc9ac1ee7844942575a520be1
author Stefan Reinauer <reinauer@chromium.org> Mon Oct 07 16:29:54 2013 -0700
committer chrome-internal-fetch <chrome-internal-fetch@google.com> Fri Oct 11 03:57:57 2013 +0000
tree 846a645a830f019bc1decff599974dc18d7de792
parent 5ef93446471589941c7bedc84bdd49a0ae3e2bbb

lynxpoint: Export pch_enable_lpc() for SuperIO systems

In order to enable a SuperIO in non ChromeEC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c

BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino

Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>

src/southbridge/intel/lynxpoint/early_pch.c

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index df7358e..a5c12bf 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -90,7 +90,7 @@
 	return is_s3;
 }
 
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
 {
 	const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 	const struct southbridge_intel_lynxpoint_config *config = NULL;

src/southbridge/intel/lynxpoint/pch.h

diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index a1a6f63..982ccb3 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -213,6 +213,7 @@
 int early_spi_read(u32 offset, u32 size, u8 *buffer);
 int early_pch_init(const void *gpio_map,
                    const struct rcba_config_instruction *rcba_config);
+void pch_enable_lpc(void);
 #endif /* !__PRE_RAM__ && !__SMM__ */
 #endif /* __ASSEMBLER__ */