diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index df7358e..a5c12bf 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -90,7 +90,7 @@
 	return is_s3;
 }
 
-static void pch_enable_lpc(void)
+void pch_enable_lpc(void)
 {
 	const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 	const struct southbridge_intel_lynxpoint_config *config = NULL;
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index a1a6f63..982ccb3 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -213,6 +213,7 @@
 int early_spi_read(u32 offset, u32 size, u8 *buffer);
 int early_pch_init(const void *gpio_map,
                    const struct rcba_config_instruction *rcba_config);
+void pch_enable_lpc(void);
 #endif /* !__PRE_RAM__ && !__SMM__ */
 #endif /* __ASSEMBLER__ */