| CONFIG_BLK_MQ_RDMA=y |
| CONFIG_CUSE=m |
| CONFIG_DCB=y |
| CONFIG_DMA_SHARED_BUFFER=y |
| CONFIG_EXTRA_FIRMWARE="" |
| CONFIG_FW_LOADER=m |
| CONFIG_FW_LOADER_PAGED_BUF=y |
| CONFIG_FW_LOADER_USER_HELPER=y |
| CONFIG_INFINIBAND=m |
| CONFIG_INFINIBAND_ON_DEMAND_PAGING=y |
| CONFIG_INFINIBAND_USER_ACCESS=m |
| CONFIG_INFINIBAND_USER_MAD=m |
| CONFIG_INFINIBAND_USER_MEM=y |
| CONFIG_INFINIBAND_VIRT_DMA=y |
| CONFIG_MLX4_CORE_GEN2=y |
| CONFIG_MLX4_CORE=m |
| CONFIG_MLX4_DEBUG=y |
| CONFIG_MLX4_EN_DCB=y |
| CONFIG_MLX4_EN=m |
| CONFIG_MLX4_INFINIBAND=m |
| CONFIG_MLX5_ACCEL=y |
| CONFIG_MLX5_CORE_EN_DCB=y |
| CONFIG_MLX5_CORE_EN=y |
| CONFIG_MLX5_CORE_IPOIB=y |
| CONFIG_MLX5_CORE=m |
| CONFIG_MLX5_EN_ARFS=y |
| CONFIG_MLX5_EN_IPSEC=y |
| CONFIG_MLX5_EN_RXNFC=y |
| CONFIG_MLX5_EN_TLS=y |
| CONFIG_MLX5_ESWITCH=y |
| CONFIG_MLX5_FPGA_IPSEC=y |
| CONFIG_MLX5_FPGA_TLS=y |
| CONFIG_MLX5_FPGA=y |
| CONFIG_MLX5_INFINIBAND=m |
| CONFIG_MLX5_MPFS=y |
| CONFIG_MLX5_SW_STEERING=y |
| CONFIG_MLX5_TLS=y |
| CONFIG_MLXFW=m |
| CONFIG_MLXSW_CORE_HWMON=y |
| CONFIG_MLXSW_CORE=m |
| CONFIG_MLXSW_CORE_THERMAL=y |
| CONFIG_MLXSW_I2C=m |
| CONFIG_MLXSW_MINIMAL=m |
| CONFIG_MLXSW_PCI=m |
| CONFIG_MLXSW_SPECTRUM_DCB=y |
| CONFIG_MLXSW_SPECTRUM=m |
| CONFIG_MLXSW_SWITCHIB=m |
| CONFIG_MLXSW_SWITCHX2=m |
| CONFIG_MMU_NOTIFIER=y |
| CONFIG_NET_DEVLINK=y |
| CONFIG_NET_SWITCHDEV=y |
| CONFIG_NET_VENDOR_MELLANOX=y |
| CONFIG_PAGE_POOL=y |
| CONFIG_PSAMPLE=m |
