blob: 8fd5e6dd3e5376c238468055cfa175ed19c58055 [file] [log] [blame]
From 120cffccf8c3a46f6003a3b5a6b0f39130df4bd2 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Fri, 16 Aug 2019 04:47:44 +0000
Subject: [PATCH] [X86] Manually reimplement getTargetInsertSubreg in
X86DAGToDAGISel::matchBitExtract so we can call insertDAGNode on the target
constant.
This is needed to maintain the topological sort order.
Fixes PR42992.
llvm-svn: 369084
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 8 ++++++--
llvm/test/CodeGen/X86/pr42992.ll | 17 +++++++++++++++++
2 files changed, 23 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/pr42992.ll
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 364f54ca5aa..46886419421 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -3333,8 +3333,12 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
SDValue ImplDef = SDValue(
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i32), 0);
insertDAGNode(*CurDAG, SDValue(Node, 0), ImplDef);
- NBits = CurDAG->getTargetInsertSubreg(X86::sub_8bit, DL, MVT::i32, ImplDef,
- NBits);
+
+ SDValue SRIdxVal = CurDAG->getTargetConstant(X86::sub_8bit, DL, MVT::i32);
+ insertDAGNode(*CurDAG, SDValue(Node, 0), SRIdxVal);
+ NBits = SDValue(
+ CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::i32, ImplDef,
+ NBits, SRIdxVal), 0);
insertDAGNode(*CurDAG, SDValue(Node, 0), NBits);
if (Subtarget->hasBMI2()) {
diff --git a/llvm/test/CodeGen/X86/pr42992.ll b/llvm/test/CodeGen/X86/pr42992.ll
new file mode 100644
index 00000000000..f85b5921b10
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr42992.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=bmi2 | FileCheck %s
+
+define i32 @hoge(i32 %a) {
+; CHECK-LABEL: hoge:
+; CHECK: # %bb.0: # %bb
+; CHECK-NEXT: movl $15, %eax
+; CHECK-NEXT: bzhil %edi, %eax, %eax
+; CHECK-NEXT: shll $8, %eax
+; CHECK-NEXT: retq
+bb:
+ %tmp3 = shl nsw i32 -1, %a
+ %tmp4 = xor i32 %tmp3, -1
+ %tmp5 = shl i32 %tmp4, 8
+ %tmp6 = and i32 %tmp5, 3840
+ ret i32 %tmp6
+}
--
2.23.0.rc1.153.gdeed80330f-goog