| commit 5ca3ef98a71598d368f6f4aaf0b385b50b67ce4a |
| Author: Simon Pilgrim <llvm-dev@redking.me.uk> |
| Date: Sat Feb 13 11:33:14 2021 +0000 |
| |
| [X86] Add reduced test case for PR49162 |
| |
| diff --git a/llvm/test/CodeGen/X86/pr49162.ll b/llvm/test/CodeGen/X86/pr49162.ll |
| new file mode 100644 |
| index 000000000000..f186dc7dbe0b |
| --- /dev/null |
| +++ b/llvm/test/CodeGen/X86/pr49162.ll |
| @@ -0,0 +1,29 @@ |
| +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| +; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86 |
| +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 |
| + |
| +define i32* @PR49162(i32* %base, i160* %ptr160) { |
| +; X86-LABEL: PR49162: |
| +; X86: # %bb.0: |
| +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax |
| +; X86-NEXT: movl 8(%eax), %ecx |
| +; X86-NEXT: shll $16, %ecx |
| +; X86-NEXT: movl %ecx, %eax |
| +; X86-NEXT: sarl $31, %eax |
| +; X86-NEXT: shldl $16, %ecx, %eax |
| +; X86-NEXT: shll $2, %eax |
| +; X86-NEXT: addl {{[0-9]+}}(%esp), %eax |
| +; X86-NEXT: retl |
| +; |
| +; X64-LABEL: PR49162: |
| +; X64: # %bb.0: |
| +; X64-NEXT: leaq -4(%rdi), %rax |
| +; X64-NEXT: retq |
| + %load160 = load i160, i160* %ptr160, align 4 |
| + %shl = shl i160 %load160, 80 |
| + %ashr160 = ashr i160 %shl, 112 |
| + %trunc = trunc i160 %ashr160 to i64 |
| + %ashr64 = ashr i64 %trunc, 32 |
| + %gep = getelementptr inbounds i32, i32* %base, i64 %ashr64 |
| + ret i32* %gep |
| +} |
