| From 2bb4ccbd95d7fbf58540c8d3d55cbabc8fb95e28 Mon Sep 17 00:00:00 2001 |
| From: Leo Yan <leo.yan@linaro.org> |
| Date: Wed, 24 Feb 2021 09:48:31 -0700 |
| Subject: [PATCH 1/5] tools headers UAPI: Update tools' copy of |
| linux/coresight-pmu.h |
| |
| To get the changes in the commit: |
| |
| "coresight: etm-perf: Clarify comment on perf options". |
| |
| Signed-off-by: Leo Yan <leo.yan@linaro.org> |
| Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> |
| Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> |
| Cc: Mike Leach <mike.leach@linaro.org> |
| Link: https://lore.kernel.org/r/20210213113220.292229-2-leo.yan@linaro.org |
| Link: https://lore.kernel.org/r/20210224164835.3497311-3-mathieu.poirier@linaro.org |
| Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com> |
| --- |
| tools/include/linux/coresight-pmu.h | 17 ++++++++++++----- |
| 1 file changed, 12 insertions(+), 5 deletions(-) |
| |
| diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h |
| index b0e35eec6499..5dc47cfdcf07 100644 |
| --- a/tools/include/linux/coresight-pmu.h |
| +++ b/tools/include/linux/coresight-pmu.h |
| @@ -10,11 +10,18 @@ |
| #define CORESIGHT_ETM_PMU_NAME "cs_etm" |
| #define CORESIGHT_ETM_PMU_SEED 0x10 |
| |
| -/* ETMv3.5/PTM's ETMCR config bit */ |
| -#define ETM_OPT_CYCACC 12 |
| -#define ETM_OPT_CTXTID 14 |
| -#define ETM_OPT_TS 28 |
| -#define ETM_OPT_RETSTK 29 |
| +/* |
| + * Below are the definition of bit offsets for perf option, and works as |
| + * arbitrary values for all ETM versions. |
| + * |
| + * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, |
| + * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and |
| + * directly use below macros as config bits. |
| + */ |
| +#define ETM_OPT_CYCACC 12 |
| +#define ETM_OPT_CTXTID 14 |
| +#define ETM_OPT_TS 28 |
| +#define ETM_OPT_RETSTK 29 |
| |
| /* ETMv4 CONFIGR programming bits for the ETM OPTs */ |
| #define ETM4_CFG_BIT_CYCACC 4 |
| -- |
| 2.32.0.rc1.229.g3e70b5a671-goog |
| |