| # Copyright 2022 The Chromium OS Authors. All rights reserved. |
| # Distributed under the terms of the GNU General Public License v2 |
| |
| EAPI=7 |
| CROS_WORKON_PROJECT="chromiumos/platform/hps-firmware" |
| CROS_WORKON_LOCALNAME="platform/hps-firmware2" |
| PYTHON_COMPAT=( python3_{6..9} ) |
| |
| inherit cros-workon cros-rust python-any-r1 |
| |
| DESCRIPTION="HPS firmware tools for development and testing" |
| HOMEPAGE="https://chromium.googlesource.com/chromiumos/platform/hps-firmware" |
| |
| LICENSE="BSD-Google" |
| KEYWORDS="~*" |
| |
| BDEPEND=" |
| dev-embedded/hps-sdk |
| dev-rust/svd2rust |
| >=sci-electronics/nextpnr-0.1_p20220210 |
| sci-electronics/nmigen |
| sci-electronics/prjoxide |
| sci-electronics/yosys |
| sci-electronics/yosys-f4pga-plugins |
| $(python_gen_any_dep ' |
| sci-electronics/litespi[${PYTHON_USEDEP}] |
| sci-electronics/litex[${PYTHON_USEDEP}] |
| sci-electronics/pythondata-cpu-vexriscv[${PYTHON_USEDEP}] |
| ') |
| " |
| |
| python_check_deps() { |
| has_version -b "sci-electronics/litespi[${PYTHON_USEDEP}]" && |
| has_version -b "sci-electronics/litex[${PYTHON_USEDEP}]" && |
| has_version -b "sci-electronics/pythondata-cpu-vexriscv[${PYTHON_USEDEP}]" |
| } |
| |
| |
| DEPEND=" |
| >=dev-rust/anyhow-1.0.38:= <dev-rust/anyhow-2.0.0 |
| >=dev-rust/bayer-0.1.5 <dev-rust/bayer-0.2.0_alpha:= |
| =dev-rust/bindgen-0.59* |
| >=dev-rust/bitflags-1.3.2:= <dev-rust/bitflags-2.0.0 |
| =dev-rust/clap-3.0.0_beta2:= |
| =dev-rust/colored-2*:= |
| >=dev-rust/cortex-m-0.7.1:= <dev-rust/cortex-m-0.8.0 |
| >=dev-rust/cortex-m-rt-0.6.13:= <dev-rust/cortex-m-rt-0.7.0 |
| >=dev-rust/cortex-m-rtic-1.1.3:= <dev-rust/cortex-m-rtic-2.0.0 |
| =dev-rust/crc-2*:= |
| >=dev-rust/defmt-0.2.1:= <dev-rust/defmt-0.3.0 |
| =dev-rust/defmt-rtt-0.2*:= |
| =dev-rust/ed25519-compact-1*:= |
| >=dev-rust/embedded-hal-0.2.4:= <dev-rust/embedded-hal-0.3.0 |
| =dev-rust/embedded-hal-mock-0.8*:= |
| >=dev-rust/hmac-sha256-0.1.6:= <dev-rust/hmac-sha256-0.2.0 |
| >=dev-rust/image-0.23.14:= <dev-rust/image-0.24 |
| >=dev-rust/indicatif-0.16.2:= <dev-rust/indicatif-0.17 |
| >=dev-rust/linux-embedded-hal-0.3.1:= <dev-rust/linux-embedded-hal-0.4 |
| >=dev-rust/log-0.4.14:= <dev-rust/log-0.5 |
| >=dev-rust/num_enum-0.5.1:= <dev-rust/num_enum-0.6.0 |
| =dev-rust/nb-1*:= |
| =dev-rust/panic-halt-0.2*:= |
| =dev-rust/panic-reset-0.1*:= |
| =dev-rust/riscv-0.7*:= |
| =dev-rust/riscv-rt-0.8*:= |
| >=dev-rust/rusb-0.8.1:= <dev-rust/rusb-0.9 |
| =dev-rust/rustyline-9*:= |
| >=dev-rust/simple_logger-1.13.0:= <dev-rust/simple_logger-2 |
| >=dev-rust/spi-memory-0.2.0:= <dev-rust/spi-memory-0.3.0 |
| =dev-rust/stm32g0xx-hal-0.1*:= |
| =dev-rust/ufmt-0.1*:= |
| =dev-rust/ufmt-write-0.1*:= |
| >=dev-rust/panic-rtt-target-0.1.2:= <dev-rust/panic-rtt-target-0.2.0 |
| >=dev-rust/rtt-target-0.3.1:= <dev-rust/rtt-target-0.4.0 |
| " |
| |
| # host tools used to live in hps-firmware |
| # hps-factory used to live in hps-firmware-images |
| RDEPEND=" |
| !<chromeos-base/hps-firmware-0.1.0-r244 |
| !<chromeos-base/hps-firmware-images-0.0.1-r28 |
| " |
| |
| src_unpack() { |
| cros-workon_src_unpack |
| cros-rust_src_unpack |
| } |
| |
| src_prepare() { |
| # Not using cros-rust_src_prepare because it wrongly assumes Cargo.toml is |
| # in the root of ${S} and we don't need its manipulations anyway. |
| |
| # config.toml is intended for use when running `cargo` directly but would |
| # mess with the ebuild if we didn't delete it. |
| rm -f rust/.cargo/config.toml |
| |
| default |
| } |
| |
| src_configure() { |
| # Use Python helper modules from CFU-Playground. These are developed |
| # upstream but are intimately tied to the HPS accelerator code. |
| export PYTHONPATH="${S}/third_party/python/CFU-Playground" |
| |
| # Use Rust from hps-sdk, since the main Chrome OS Rust compiler |
| # does not yet support RISC-V. |
| export PATH="/opt/hps-sdk/bin:${PATH}" |
| |
| # CROS_BASE_RUSTFLAGS are for the AP, they are not applicable to |
| # HPS firmware, which is cross-compiled for STM32 |
| unset CROS_BASE_RUSTFLAGS |
| cros-rust_configure_cargo |
| |
| # Override some unwanted rustflags configured by cros-rust_configure_cargo. |
| # For our Cortex-M0 target, we need "fat" LTO and opt-level=z (smallest) to |
| # make everything small enough to fit. Debug assertions and |
| # integer overflow checks introduce panicking paths into the firmware, |
| # which bloats the size of the images with extra strings in .rodata. |
| # TODO(dcallagh): tidy this up properly in cros-rust.eclass. |
| # CROS_BASE_RUSTFLAGS are the same problem. |
| # asan and ubsan are also the same problem. |
| # shellcheck disable=SC2154 # ECARGO_HOME is defined in cros-rust.eclass |
| cat <<- EOF >> "${ECARGO_HOME}/config" |
| [target.'cfg(all(target_arch = "arm", target_os = "none"))'] |
| rustflags = [ |
| "-Clto=yes", |
| "-Copt-level=z", |
| "-Coverflow-checks=off", |
| "-Cdebug-assertions=off", |
| "-Ccodegen-units=1", |
| ] |
| EOF |
| |
| # cros-rust_update_cargo_lock tries to handle Cargo.lock but it assumes |
| # there is only one Cargo.lock in the root of the source tree, which is not |
| # true for hps-firmware. For now just delete the ones we have. |
| rm rust/Cargo.lock rust/mcu/Cargo.lock rust/riscv/Cargo.lock |
| } |
| |
| src_compile() { |
| # hps-factory needs an FPGA bitstream. |
| einfo "Building FPGA bitstream" |
| python -m soc.hps_soc || die |
| |
| for tool in hps-factory hps-mon hps-util ; do ( |
| cd rust/${tool} || die |
| einfo "Building ${tool}" |
| ecargo_build |
| ) done |
| } |
| |
| src_test() { |
| # The hps-firmware ebuild runs all unit tests (including for host tools), |
| # nothing more to do here. |
| : |
| } |
| |
| src_install() { |
| dobin "$(cros-rust_get_build_dir)/hps-factory" |
| dobin "$(cros-rust_get_build_dir)/hps-mon" |
| dobin "$(cros-rust_get_build_dir)/hps-util" |
| } |