| From 8f361b9db6ddda8dab99627be40d3e3867ae3fa9 Mon Sep 17 00:00:00 2001 |
| From: Kevin Strasser <kevin.strasser@intel.com> |
| Date: Fri, 12 Jul 2019 13:25:14 -0700 |
| Subject: [PATCH 02/13] BACKPORT: i965: Add helper function for allowed config |
| formats |
| |
| The driver checks dri config options and loader caps to filter out certain |
| formats during config creation. Fold 4 call sites under a single helper |
| function. |
| |
| Signed-off-by: Kevin Strasser <kevin.strasser@intel.com> |
| Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> |
| (cherry picked from commit 4fb71604b7a60b94bd647c3ccd0140e1c3b1e083) |
| |
| Conflicts:Drop rgb565 format code from intel_allowed_format. |
| src/mesa/drivers/dri/i965/intel_screen.c |
| |
| Change-Id: Ieef59fdae574b8699f3285a78008338effe961ca |
| --- |
| src/mesa/drivers/dri/i965/intel_screen.c | 47 ++++++++++++++---------- |
| 1 file changed, 28 insertions(+), 19 deletions(-) |
| |
| diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c |
| index 8838f977bb6..97a62aa1591 100644 |
| --- a/src/mesa/drivers/dri/i965/intel_screen.c |
| +++ b/src/mesa/drivers/dri/i965/intel_screen.c |
| @@ -2112,6 +2112,30 @@ intel_loader_get_cap(const __DRIscreen *dri_screen, enum dri_loader_cap cap) |
| return 0; |
| } |
| |
| +static bool |
| +intel_allowed_format(__DRIscreen *dri_screen, mesa_format format) |
| +{ |
| + struct intel_screen *screen = dri_screen->driverPrivate; |
| + |
| + /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */ |
| + bool allow_rgba_ordering = intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING); |
| + if (!allow_rgba_ordering && |
| + (format == MESA_FORMAT_R8G8B8A8_UNORM || |
| + format == MESA_FORMAT_R8G8B8X8_UNORM || |
| + format == MESA_FORMAT_R8G8B8A8_SRGB)) |
| + return false; |
| + |
| + /* Shall we expose 10 bpc formats? */ |
| + bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, |
| + "allow_rgb10_configs"); |
| + if (!allow_rgb10_configs && |
| + (format == MESA_FORMAT_B10G10R10A2_UNORM || |
| + format == MESA_FORMAT_B10G10R10X2_UNORM)) |
| + return false; |
| + |
| + return true; |
| +} |
| + |
| static __DRIconfig** |
| intel_screen_make_configs(__DRIscreen *dri_screen) |
| { |
| @@ -2162,16 +2186,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) |
| uint8_t depth_bits[4], stencil_bits[4]; |
| __DRIconfig **configs = NULL; |
| |
| - /* Expose only BGRA ordering if the loader doesn't support RGBA ordering. */ |
| - unsigned num_formats; |
| - if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING)) |
| - num_formats = ARRAY_SIZE(formats); |
| - else |
| - num_formats = ARRAY_SIZE(formats) - 3; /* all - RGBA_ORDERING formats */ |
| - |
| - /* Shall we expose 10 bpc formats? */ |
| - bool allow_rgb10_configs = driQueryOptionb(&screen->optionCache, |
| - "allow_rgb10_configs"); |
| + unsigned num_formats = ARRAY_SIZE(formats); |
| |
| /* Generate singlesample configs, each without accumulation buffer |
| * and with EGL_MUTABLE_RENDER_BUFFER_BIT_KHR. |
| @@ -2180,9 +2195,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) |
| __DRIconfig **new_configs; |
| int num_depth_stencil_bits = 2; |
| |
| - if (!allow_rgb10_configs && |
| - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || |
| - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) |
| + if (!intel_allowed_format(dri_screen, formats[i])) |
| continue; |
| |
| /* Starting with DRI2 protocol version 1.1 we can request a depth/stencil |
| @@ -2222,9 +2235,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) |
| for (unsigned i = 0; i < num_formats; i++) { |
| __DRIconfig **new_configs; |
| |
| - if (!allow_rgb10_configs && |
| - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || |
| - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) |
| + if (!intel_allowed_format(dri_screen, formats[i])) |
| continue; |
| |
| if (formats[i] == MESA_FORMAT_B5G6R5_UNORM) { |
| @@ -2260,9 +2271,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen) |
| if (devinfo->gen < 6) |
| break; |
| |
| - if (!allow_rgb10_configs && |
| - (formats[i] == MESA_FORMAT_B10G10R10A2_UNORM || |
| - formats[i] == MESA_FORMAT_B10G10R10X2_UNORM)) |
| + if (!intel_allowed_format(dri_screen, formats[i])) |
| continue; |
| |
| __DRIconfig **new_configs; |
| -- |
| 2.21.0 |
| |