| DEFINED_PHASES=configure test unpack |
| DESCRIPTION=A framework for Verilog RTL synthesis. |
| EAPI=7 |
| HOMEPAGE=http://www.clifford.at/yosys/ |
| KEYWORDS=* |
| LICENSE=ISC |
| RDEPEND=sci-electronics/iverilog |
| SLOT=0 |
| SRC_URI=https://github.com/YosysHQ/yosys/archive/1cac671c70bc3da9808ceb3add15686da4a5d82e.tar.gz -> yosys-1cac671c70bc3da9808ceb3add15686da4a5d82e.tar.gz https://github.com/YosysHQ/abc/archive/4f5f73d.tar.gz -> yosys-abc-4f5f73d.tar.gz |
| _eclasses_=eutils fcb2aa98e1948b835b5ae66ca52868c5 flag-o-matic 5d5921a298e95441da2f85be419894c0 multilib 2477ebe553d3e4d2c606191fe6c33602 toolchain-funcs 528ab0a9e1ee02c57524ad3bede3c57e |
| _md5_=01916ec836c11dc3cd8c03bc4c3f8bbb |
