| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2021 MediaTek Inc. |
| * Author: Sam.Shih <sam.shih@mediatek.com> |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/mt7986-clk.h> |
| #include <dt-bindings/reset/mt7986-resets.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| clk40m: oscillator-40m { |
| compatible = "fixed-clock"; |
| clock-frequency = <40000000>; |
| #clock-cells = <0>; |
| clock-output-names = "clkxtal"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x0>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x1>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x2>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| enable-method = "psci"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x3>; |
| #cooling-cells = <2>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| secmon_reserved: secmon@43000000 { |
| reg = <0 0x43000000 0 0x30000>; |
| no-map; |
| }; |
| |
| wmcpu_emi: wmcpu-reserved@4fc00000 { |
| no-map; |
| reg = <0 0x4fc00000 0 0x00100000>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| compatible = "simple-bus"; |
| ranges; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&gic>; |
| interrupt-controller; |
| reg = <0 0x0c000000 0 0x10000>, /* GICD */ |
| <0 0x0c080000 0 0x80000>, /* GICR */ |
| <0 0x0c400000 0 0x2000>, /* GICC */ |
| <0 0x0c410000 0 0x1000>, /* GICH */ |
| <0 0x0c420000 0 0x2000>; /* GICV */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| infracfg: infracfg@10001000 { |
| compatible = "mediatek,mt7986-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| wed_pcie: wed-pcie@10003000 { |
| compatible = "mediatek,mt7986-wed-pcie", |
| "syscon"; |
| reg = <0 0x10003000 0 0x10>; |
| }; |
| |
| topckgen: topckgen@1001b000 { |
| compatible = "mediatek,mt7986-topckgen", "syscon"; |
| reg = <0 0x1001B000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| watchdog: watchdog@1001c000 { |
| compatible = "mediatek,mt7986-wdt"; |
| reg = <0 0x1001c000 0 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| #reset-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| apmixedsys: apmixedsys@1001e000 { |
| compatible = "mediatek,mt7986-apmixedsys"; |
| reg = <0 0x1001E000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pio: pinctrl@1001f000 { |
| compatible = "mediatek,mt7986a-pinctrl"; |
| reg = <0 0x1001f000 0 0x1000>, |
| <0 0x11c30000 0 0x1000>, |
| <0 0x11c40000 0 0x1000>, |
| <0 0x11e20000 0 0x1000>, |
| <0 0x11e30000 0 0x1000>, |
| <0 0x11f00000 0 0x1000>, |
| <0 0x11f10000 0 0x1000>, |
| <0 0x1000b000 0 0x1000>; |
| reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", |
| "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&pio 0 0 100>; |
| interrupt-controller; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| #interrupt-cells = <2>; |
| }; |
| |
| sgmiisys0: syscon@10060000 { |
| compatible = "mediatek,mt7986-sgmiisys_0", |
| "syscon"; |
| reg = <0 0x10060000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| sgmiisys1: syscon@10070000 { |
| compatible = "mediatek,mt7986-sgmiisys_1", |
| "syscon"; |
| reg = <0 0x10070000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| trng: rng@1020f000 { |
| compatible = "mediatek,mt7986-rng", |
| "mediatek,mt7623-rng"; |
| reg = <0 0x1020f000 0 0x100>; |
| clocks = <&infracfg CLK_INFRA_TRNG_CK>; |
| clock-names = "rng"; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@11002000 { |
| compatible = "mediatek,mt7986-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x400>; |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg CLK_INFRA_UART0_SEL>, |
| <&infracfg CLK_INFRA_UART0_CK>; |
| clock-names = "baud", "bus"; |
| assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, |
| <&infracfg CLK_INFRA_UART0_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, |
| <&topckgen CLK_TOP_UART_SEL>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@11003000 { |
| compatible = "mediatek,mt7986-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x400>; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg CLK_INFRA_UART1_SEL>, |
| <&infracfg CLK_INFRA_UART1_CK>; |
| clock-names = "baud", "bus"; |
| assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@11004000 { |
| compatible = "mediatek,mt7986-uart", |
| "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x400>; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg CLK_INFRA_UART2_SEL>, |
| <&infracfg CLK_INFRA_UART2_CK>; |
| clock-names = "baud", "bus"; |
| assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; |
| assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; |
| status = "disabled"; |
| }; |
| |
| ethsys: syscon@15000000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "mediatek,mt7986-ethsys", |
| "syscon"; |
| reg = <0 0x15000000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| wed0: wed@15010000 { |
| compatible = "mediatek,mt7986-wed", |
| "syscon"; |
| reg = <0 0x15010000 0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| wed1: wed@15011000 { |
| compatible = "mediatek,mt7986-wed", |
| "syscon"; |
| reg = <0 0x15011000 0 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| eth: ethernet@15100000 { |
| compatible = "mediatek,mt7986-eth"; |
| reg = <0 0x15100000 0 0x80000>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <ðsys CLK_ETH_FE_EN>, |
| <ðsys CLK_ETH_GP2_EN>, |
| <ðsys CLK_ETH_GP1_EN>, |
| <ðsys CLK_ETH_WOCPU1_EN>, |
| <ðsys CLK_ETH_WOCPU0_EN>, |
| <&sgmiisys0 CLK_SGMII0_TX250M_EN>, |
| <&sgmiisys0 CLK_SGMII0_RX250M_EN>, |
| <&sgmiisys0 CLK_SGMII0_CDR_REF>, |
| <&sgmiisys0 CLK_SGMII0_CDR_FB>, |
| <&sgmiisys1 CLK_SGMII1_TX250M_EN>, |
| <&sgmiisys1 CLK_SGMII1_RX250M_EN>, |
| <&sgmiisys1 CLK_SGMII1_CDR_REF>, |
| <&sgmiisys1 CLK_SGMII1_CDR_FB>, |
| <&topckgen CLK_TOP_NETSYS_SEL>, |
| <&topckgen CLK_TOP_NETSYS_500M_SEL>; |
| clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", |
| "sgmii_tx250m", "sgmii_rx250m", |
| "sgmii_cdr_ref", "sgmii_cdr_fb", |
| "sgmii2_tx250m", "sgmii2_rx250m", |
| "sgmii2_cdr_ref", "sgmii2_cdr_fb", |
| "netsys0", "netsys1"; |
| assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, |
| <&topckgen CLK_TOP_SGM_325M_SEL>; |
| assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, |
| <&apmixedsys CLK_APMIXED_SGMPLL>; |
| mediatek,ethsys = <ðsys>; |
| mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| mediatek,wed-pcie = <&wed_pcie>; |
| mediatek,wed = <&wed0>, <&wed1>; |
| #reset-cells = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| wifi: wifi@18000000 { |
| compatible = "mediatek,mt7986-wmac"; |
| resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; |
| reset-names = "consys"; |
| clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, |
| <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; |
| clock-names = "mcu", "ap2conn"; |
| reg = <0 0x18000000 0 0x1000000>, |
| <0 0x10003000 0 0x1000>, |
| <0 0x11d10000 0 0x1000>; |
| interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| memory-region = <&wmcpu_emi>; |
| }; |
| }; |
| |
| }; |
