arch/arm/boot/dts/imx6q.dtsi - third_party/kernel - Git at Google

 // SPDX-License-Identifier: GPL-2.0
 //
 // Copyright 2013 Freescale Semiconductor, Inc.

 #include <dt-bindings/interrupt-controller/irq.h>
 #include "imx6q-pinfunc.h"
 #include "imx6qdl.dtsi"

 / {
 	aliases {
 		ipu1 = &ipu2;
 		spi4 = &ecspi5;
 	};

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu0: cpu@0 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
 			operating-points = <
 				/* kHz    uV */
 				1200000 1275000
 				996000  1250000
 				852000  1250000
 				792000  1175000
 				396000  975000
 			>;
 			fsl,soc-operating-points = <
 				/* ARM kHz  SOC-PU uV */
 				1200000 1275000
 				996000	1250000
 				852000	1250000
 				792000	1175000
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
 			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
 				 <&clks IMX6QDL_CLK_PLL1_SW>,
 				 <&clks IMX6QDL_CLK_PLL1_SYS>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
 				      "pll1_sw", "pll1_sys";
 			arm-supply = <&reg_arm>;
 			pu-supply = <&reg_pu>;
 			soc-supply = <&reg_soc>;
 			nvmem-cells = <&cpu_speed_grade>;
 			nvmem-cell-names = "speed_grade";
 		};

 		cpu1: cpu@1 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
 			operating-points = <
 				/* kHz    uV */
 				1200000 1275000
 				996000  1250000
 				852000  1250000
 				792000  1175000
 				396000  975000
 			>;
 			fsl,soc-operating-points = <
 				/* ARM kHz  SOC-PU uV */
 				1200000 1275000
 				996000	1250000
 				852000	1250000
 				792000	1175000
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
 			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
 				 <&clks IMX6QDL_CLK_PLL1_SW>,
 				 <&clks IMX6QDL_CLK_PLL1_SYS>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
 				      "pll1_sw", "pll1_sys";
 			arm-supply = <&reg_arm>;
 			pu-supply = <&reg_pu>;
 			soc-supply = <&reg_soc>;
 		};

 		cpu2: cpu@2 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <2>;
 			next-level-cache = <&L2>;
 			operating-points = <
 				/* kHz    uV */
 				1200000 1275000
 				996000  1250000
 				852000  1250000
 				792000  1175000
 				396000  975000
 			>;
 			fsl,soc-operating-points = <
 				/* ARM kHz  SOC-PU uV */
 				1200000 1275000
 				996000	1250000
 				852000	1250000
 				792000	1175000
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
 			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
 				 <&clks IMX6QDL_CLK_PLL1_SW>,
 				 <&clks IMX6QDL_CLK_PLL1_SYS>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
 				      "pll1_sw", "pll1_sys";
 			arm-supply = <&reg_arm>;
 			pu-supply = <&reg_pu>;
 			soc-supply = <&reg_soc>;
 		};

 		cpu3: cpu@3 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <3>;
 			next-level-cache = <&L2>;
 			operating-points = <
 				/* kHz    uV */
 				1200000 1275000
 				996000  1250000
 				852000  1250000
 				792000  1175000
 				396000  975000
 			>;
 			fsl,soc-operating-points = <
 				/* ARM kHz  SOC-PU uV */
 				1200000 1275000
 				996000	1250000
 				852000	1250000
 				792000	1175000
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
 			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
 				 <&clks IMX6QDL_CLK_PLL1_SW>,
 				 <&clks IMX6QDL_CLK_PLL1_SYS>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
 				      "pll1_sw", "pll1_sys";
 			arm-supply = <&reg_arm>;
 			pu-supply = <&reg_pu>;
 			soc-supply = <&reg_soc>;
 		};
 	};

 	soc {
 		ocram: sram@900000 {
 			compatible = "mmio-sram";
 			reg = <0x00900000 0x40000>;
 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
 		};

 		bus@2000000 { /* AIPS1 */
 			spba-bus@2000000 {
 				ecspi5: spi@2018000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 					reg = <0x02018000 0x4000>;
 					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 					clocks = <&clks IMX6Q_CLK_ECSPI5>,
 						 <&clks IMX6Q_CLK_ECSPI5>;
 					clock-names = "ipg", "per";
 					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 			};
 		};

 		sata: sata@2200000 {
 			compatible = "fsl,imx6q-ahci";
 			reg = <0x02200000 0x4000>;
 			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_SATA>,
 				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
 				 <&clks IMX6QDL_CLK_AHB>;
 			clock-names = "sata", "sata_ref", "ahb";
 			status = "disabled";
 		};

 		gpu_vg: gpu@2204000 {
 			compatible = "vivante,gc";
 			reg = <0x02204000 0x4000>;
 			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
 				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
 			clock-names = "bus", "core";
 			power-domains = <&pd_pu>;
 			#cooling-cells = <2>;
 		};

 		ipu2: ipu@2800000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			compatible = "fsl,imx6q-ipu";
 			reg = <0x02800000 0x400000>;
 			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_IPU2>,
 				 <&clks IMX6QDL_CLK_IPU2_DI0>,
 				 <&clks IMX6QDL_CLK_IPU2_DI1>;
 			clock-names = "bus", "di0", "di1";
 			resets = <&src 4>;

 			ipu2_csi0: port@0 {
 				reg = <0>;

 				ipu2_csi0_from_mipi_vc2: endpoint {
 					remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
 				};
 			};

 			ipu2_csi1: port@1 {
 				reg = <1>;

 				ipu2_csi1_from_ipu2_csi1_mux: endpoint {
 					remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
 				};
 			};

 			ipu2_di0: port@2 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <2>;

 				ipu2_di0_disp0: endpoint@0 {
 					reg = <0>;
 				};

 				ipu2_di0_hdmi: endpoint@1 {
 					reg = <1>;
 					remote-endpoint = <&hdmi_mux_2>;
 				};

 				ipu2_di0_mipi: endpoint@2 {
 					reg = <2>;
 					remote-endpoint = <&mipi_mux_2>;
 				};

 				ipu2_di0_lvds0: endpoint@3 {
 					reg = <3>;
 					remote-endpoint = <&lvds0_mux_2>;
 				};

 				ipu2_di0_lvds1: endpoint@4 {
 					reg = <4>;
 					remote-endpoint = <&lvds1_mux_2>;
 				};
 			};

 			ipu2_di1: port@3 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				reg = <3>;

 				ipu2_di1_hdmi: endpoint@1 {
 					reg = <1>;
 					remote-endpoint = <&hdmi_mux_3>;
 				};

 				ipu2_di1_mipi: endpoint@2 {
 					reg = <2>;
 					remote-endpoint = <&mipi_mux_3>;
 				};

 				ipu2_di1_lvds0: endpoint@3 {
 					reg = <3>;
 					remote-endpoint = <&lvds0_mux_3>;
 				};

 				ipu2_di1_lvds1: endpoint@4 {
 					reg = <4>;
 					remote-endpoint = <&lvds1_mux_3>;
 				};
 			};
 		};
 	};

 	capture-subsystem {
 		compatible = "fsl,imx-capture-subsystem";
 		ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
 	};

 	display-subsystem {
 		compatible = "fsl,imx-display-subsystem";
 		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 	};
 };

 &gpio1 {
 	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
 		      <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
 		      <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
 		      <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
 		      <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
 		      <&iomuxc 22 116 10>;
 };

 &gpio2 {
 	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
 		      <&iomuxc 31  44  1>;
 };

 &gpio3 {
 	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
 };

 &gpio4 {
 	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
 };

 &gpio5 {
 	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
 		      <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
 };

 &gpio6 {
 	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
 		      <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
 		      <&iomuxc 31  86 1>;
 };

 &gpio7 {
 	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
 };

 &gpr {
 	ipu1_csi0_mux {
 		compatible = "video-mux";
 		mux-controls = <&mux 0>;
 		#address-cells = <1>;
 		#size-cells = <0>;

 		port@0 {
 			reg = <0>;

 			ipu1_csi0_mux_from_mipi_vc0: endpoint {
 				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 			};
 		};

 		port@1 {
 			reg = <1>;

 			ipu1_csi0_mux_from_parallel_sensor: endpoint {
 			};
 		};

 		port@2 {
 			reg = <2>;

 			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 			};
 		};
 	};

 	ipu2_csi1_mux {
 		compatible = "video-mux";
 		mux-controls = <&mux 1>;
 		#address-cells = <1>;
 		#size-cells = <0>;

 		port@0 {
 			reg = <0>;

 			ipu2_csi1_mux_from_mipi_vc3: endpoint {
 				remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
 			};
 		};

 		port@1 {
 			reg = <1>;

 			ipu2_csi1_mux_from_parallel_sensor: endpoint {
 			};
 		};

 		port@2 {
 			reg = <2>;

 			ipu2_csi1_mux_to_ipu2_csi1: endpoint {
 				remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
 			};
 		};
 	};
 };

 &hdmi {
 	compatible = "fsl,imx6q-hdmi";

 	ports {
 		port@2 {
 			reg = <2>;

 			hdmi_mux_2: endpoint {
 				remote-endpoint = <&ipu2_di0_hdmi>;
 			};
 		};

 		port@3 {
 			reg = <3>;

 			hdmi_mux_3: endpoint {
 				remote-endpoint = <&ipu2_di1_hdmi>;
 			};
 		};
 	};
 };

 &iomuxc {
 	compatible = "fsl,imx6q-iomuxc";
 };

 &ipu1_csi1 {
 	ipu1_csi1_from_mipi_vc1: endpoint {
 		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
 	};
 };

 &ldb {
 	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
 		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 	clock-names = "di0_pll", "di1_pll",
 		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 		      "di0", "di1";

 	lvds-channel@0 {
 		port@2 {
 			reg = <2>;

 			lvds0_mux_2: endpoint {
 				remote-endpoint = <&ipu2_di0_lvds0>;
 			};
 		};

 		port@3 {
 			reg = <3>;

 			lvds0_mux_3: endpoint {
 				remote-endpoint = <&ipu2_di1_lvds0>;
 			};
 		};
 	};

 	lvds-channel@1 {
 		port@2 {
 			reg = <2>;

 			lvds1_mux_2: endpoint {
 				remote-endpoint = <&ipu2_di0_lvds1>;
 			};
 		};

 		port@3 {
 			reg = <3>;

 			lvds1_mux_3: endpoint {
 				remote-endpoint = <&ipu2_di1_lvds1>;
 			};
 		};
 	};
 };

 &mipi_csi {
 	port@1 {
 		reg = <1>;

 		mipi_vc0_to_ipu1_csi0_mux: endpoint {
 			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 		};
 	};

 	port@2 {
 		reg = <2>;

 		mipi_vc1_to_ipu1_csi1: endpoint {
 			remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
 		};
 	};

 	port@3 {
 		reg = <3>;

 		mipi_vc2_to_ipu2_csi0: endpoint {
 			remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
 		};
 	};

 	port@4 {
 		reg = <4>;

 		mipi_vc3_to_ipu2_csi1_mux: endpoint {
 			remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
 		};
 	};
 };

 &mipi_dsi {
 	ports {
 		port@2 {
 			reg = <2>;

 			mipi_mux_2: endpoint {
 				remote-endpoint = <&ipu2_di0_mipi>;
 			};
 		};

 		port@3 {
 			reg = <3>;

 			mipi_mux_3: endpoint {
 				remote-endpoint = <&ipu2_di1_mipi>;
 			};
 		};
 	};
 };

 &mux {
 	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
 			<0x04 0x00100000>, /* MIPI_IPU2_MUX */
 			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
 			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 };

 &vpu {
 	compatible = "fsl,imx6q-vpu", "cnm,coda960";
 };
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2013 Freescale Semiconductor, Inc.

	#include <dt-bindings/interrupt-controller/irq.h>
	#include "imx6q-pinfunc.h"
	#include "imx6qdl.dtsi"

	/ {
	aliases {
	ipu1 = &ipu2;
	spi4 = &ecspi5;
	};

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <0>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	nvmem-cells = <&cpu_speed_grade>;
	nvmem-cell-names = "speed_grade";
	};

	cpu1: cpu@1 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <1>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	};

	cpu2: cpu@2 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <2>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	};

	cpu3: cpu@3 {
	compatible = "arm,cortex-a9";
	device_type = "cpu";
	reg = <3>;
	next-level-cache = <&L2>;
	operating-points = <
	/* kHz uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 975000
	>;
	fsl,soc-operating-points = <
	/* ARM kHz SOC-PU uV */
	1200000 1275000
	996000 1250000
	852000 1250000
	792000 1175000
	396000 1175000
	>;
	clock-latency = <61036>; /* two CLK32 periods */
	#cooling-cells = <2>;
	clocks = <&clks IMX6QDL_CLK_ARM>,
	<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
	<&clks IMX6QDL_CLK_STEP>,
	<&clks IMX6QDL_CLK_PLL1_SW>,
	<&clks IMX6QDL_CLK_PLL1_SYS>;
	clock-names = "arm", "pll2_pfd2_396m", "step",
	"pll1_sw", "pll1_sys";
	arm-supply = <&reg_arm>;
	pu-supply = <&reg_pu>;
	soc-supply = <&reg_soc>;
	};
	};

	soc {
	ocram: sram@900000 {
	compatible = "mmio-sram";
	reg = <0x00900000 0x40000>;
	clocks = <&clks IMX6QDL_CLK_OCRAM>;
	};

	bus@2000000 { /* AIPS1 */
	spba-bus@2000000 {
	ecspi5: spi@2018000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
	reg = <0x02018000 0x4000>;
	interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6Q_CLK_ECSPI5>,
	<&clks IMX6Q_CLK_ECSPI5>;
	clock-names = "ipg", "per";
	dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
	dma-names = "rx", "tx";
	status = "disabled";
	};
	};
	};

	sata: sata@2200000 {
	compatible = "fsl,imx6q-ahci";
	reg = <0x02200000 0x4000>;
	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_SATA>,
	<&clks IMX6QDL_CLK_SATA_REF_100M>,
	<&clks IMX6QDL_CLK_AHB>;
	clock-names = "sata", "sata_ref", "ahb";
	status = "disabled";
	};

	gpu_vg: gpu@2204000 {
	compatible = "vivante,gc";
	reg = <0x02204000 0x4000>;
	interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
	<&clks IMX6QDL_CLK_GPU2D_CORE>;
	clock-names = "bus", "core";
	power-domains = <&pd_pu>;
	#cooling-cells = <2>;
	};

	ipu2: ipu@2800000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "fsl,imx6q-ipu";
	reg = <0x02800000 0x400000>;
	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
	<0 7 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&clks IMX6QDL_CLK_IPU2>,
	<&clks IMX6QDL_CLK_IPU2_DI0>,
	<&clks IMX6QDL_CLK_IPU2_DI1>;
	clock-names = "bus", "di0", "di1";
	resets = <&src 4>;

	ipu2_csi0: port@0 {
	reg = <0>;

	ipu2_csi0_from_mipi_vc2: endpoint {
	remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
	};
	};

	ipu2_csi1: port@1 {
	reg = <1>;

	ipu2_csi1_from_ipu2_csi1_mux: endpoint {
	remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
	};
	};

	ipu2_di0: port@2 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <2>;

	ipu2_di0_disp0: endpoint@0 {
	reg = <0>;
	};

	ipu2_di0_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_mux_2>;
	};

	ipu2_di0_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_mux_2>;
	};

	ipu2_di0_lvds0: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds0_mux_2>;
	};

	ipu2_di0_lvds1: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&lvds1_mux_2>;
	};
	};

	ipu2_di1: port@3 {
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <3>;

	ipu2_di1_hdmi: endpoint@1 {
	reg = <1>;
	remote-endpoint = <&hdmi_mux_3>;
	};

	ipu2_di1_mipi: endpoint@2 {
	reg = <2>;
	remote-endpoint = <&mipi_mux_3>;
	};

	ipu2_di1_lvds0: endpoint@3 {
	reg = <3>;
	remote-endpoint = <&lvds0_mux_3>;
	};

	ipu2_di1_lvds1: endpoint@4 {
	reg = <4>;
	remote-endpoint = <&lvds1_mux_3>;
	};
	};
	};
	};

	capture-subsystem {
	compatible = "fsl,imx-capture-subsystem";
	ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
	};

	display-subsystem {
	compatible = "fsl,imx-display-subsystem";
	ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
	};
	};

	&gpio1 {
	gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
	<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
	<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
	<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
	<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
	<&iomuxc 22 116 10>;
	};

	&gpio2 {
	gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
	<&iomuxc 31 44 1>;
	};

	&gpio3 {
	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
	};

	&gpio4 {
	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
	};

	&gpio5 {
	gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
	<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
	};

	&gpio6 {
	gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
	<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
	<&iomuxc 31 86 1>;
	};

	&gpio7 {
	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
	};

	&gpr {
	ipu1_csi0_mux {
	compatible = "video-mux";
	mux-controls = <&mux 0>;
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	ipu1_csi0_mux_from_mipi_vc0: endpoint {
	remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
	};
	};

	port@1 {
	reg = <1>;

	ipu1_csi0_mux_from_parallel_sensor: endpoint {
	};
	};

	port@2 {
	reg = <2>;

	ipu1_csi0_mux_to_ipu1_csi0: endpoint {
	remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
	};
	};
	};

	ipu2_csi1_mux {
	compatible = "video-mux";
	mux-controls = <&mux 1>;
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;

	ipu2_csi1_mux_from_mipi_vc3: endpoint {
	remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
	};
	};

	port@1 {
	reg = <1>;

	ipu2_csi1_mux_from_parallel_sensor: endpoint {
	};
	};

	port@2 {
	reg = <2>;

	ipu2_csi1_mux_to_ipu2_csi1: endpoint {
	remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
	};
	};
	};
	};

	&hdmi {
	compatible = "fsl,imx6q-hdmi";

	ports {
	port@2 {
	reg = <2>;

	hdmi_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_hdmi>;
	};
	};

	port@3 {
	reg = <3>;

	hdmi_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_hdmi>;
	};
	};
	};
	};

	&iomuxc {
	compatible = "fsl,imx6q-iomuxc";
	};

	&ipu1_csi1 {
	ipu1_csi1_from_mipi_vc1: endpoint {
	remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
	};
	};

	&ldb {
	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
	<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
	<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
	<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
	clock-names = "di0_pll", "di1_pll",
	"di0_sel", "di1_sel", "di2_sel", "di3_sel",
	"di0", "di1";

	lvds-channel@0 {
	port@2 {
	reg = <2>;

	lvds0_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_lvds0>;
	};
	};

	port@3 {
	reg = <3>;

	lvds0_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_lvds0>;
	};
	};
	};

	lvds-channel@1 {
	port@2 {
	reg = <2>;

	lvds1_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_lvds1>;
	};
	};

	port@3 {
	reg = <3>;

	lvds1_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_lvds1>;
	};
	};
	};
	};

	&mipi_csi {
	port@1 {
	reg = <1>;

	mipi_vc0_to_ipu1_csi0_mux: endpoint {
	remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
	};
	};

	port@2 {
	reg = <2>;

	mipi_vc1_to_ipu1_csi1: endpoint {
	remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
	};
	};

	port@3 {
	reg = <3>;

	mipi_vc2_to_ipu2_csi0: endpoint {
	remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
	};
	};

	port@4 {
	reg = <4>;

	mipi_vc3_to_ipu2_csi1_mux: endpoint {
	remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
	};
	};
	};

	&mipi_dsi {
	ports {
	port@2 {
	reg = <2>;

	mipi_mux_2: endpoint {
	remote-endpoint = <&ipu2_di0_mipi>;
	};
	};

	port@3 {
	reg = <3>;

	mipi_mux_3: endpoint {
	remote-endpoint = <&ipu2_di1_mipi>;
	};
	};
	};
	};

	&mux {
	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
	<0x04 0x00100000>, /* MIPI_IPU2_MUX */
	<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
	<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
	<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
	<0x28 0x00000003>, /* DCIC1_MUX_CTL */
	<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
	};

	&vpu {
	compatible = "fsl,imx6q-vpu", "cnm,coda960";
	};