arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi

// SPDX-License-Identifier: ISC
/*
 * Device Tree include file for Intel reference designs for the
 * XScale Network Processors in the IXP 4xx series. Common device
 * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
 */

/ {
	memory@0 {
		/*
		 * The board supports up to 256 MB of memory. Here we put in
		 * 64 MB and this may be modified by the boot loader.
		 */
		device_type = "memory";
		reg = <0x00000000 0x4000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		eeprom@50 {
			/*
			 * Philips PCF8582C-2T/03 512byte I2C EEPROM
			 * should behave like an Atmel 24c04.
			 */
			compatible = "atmel,24c04";
			reg = <0x50>;
			pagesize = <16>;
			size = <512>;
			read-only;
		};
	};

	soc {
		bus@c4000000 {
			/* Flash memory defined per-variant */
			nand-controller@3,0 {
				/* Some designs have a NAND on CS3 enable it here if present */
				status = "disabled";

				/*
				 * gen_nand needs to be extended and documented to get
				 * command byte = 1 and address byte = 2 from the device
				 * tree.
				 */
				compatible = "gen_nand";

				/* Expansion bus set-up */
				intel,ixp4xx-eb-t1 = <0>;
				intel,ixp4xx-eb-t2 = <0>;
				intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
				intel,ixp4xx-eb-t4 = <0>;
				intel,ixp4xx-eb-t5 = <0>;
				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
				intel,ixp4xx-eb-byte-access-on-halfword = <0>;
				intel,ixp4xx-eb-mux-address-and-data = <0>;
				intel,ixp4xx-eb-ahb-split-transfers = <0>;
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;

				/* 512 bytes memory window */
				reg = <3 0x00000000 0x200>;
				nand-on-flash-bbt;
				nand-ecc-mode = "soft_bch";
				nand-ecc-step-size = <512>;
				nand-ecc-strength = <4>;
				nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */

				label = "ixp400 NAND";

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <1>;
					#size-cells = <1>;

					fs@0 {
						label = "ixp400 NAND FS 0";
						reg = <0x0 0x800000>;
					};
					fs@800000 {
						label = "ixp400 NAND FS 1";
						reg = <0x800000 0x0>;
					};
				};
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * Taken from IXDP425 PCI boardfile.
			 * PCI slots on the BIXMB425BD base card.
			 * We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
			 */
			#interrupt-cells = <1>;
			interrupt-map-mask = <0xf800 0 0 7>;
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
			<0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
			<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
			<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
			/* IDSEL 4 */
			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
			<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
			<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
			<0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
		};
	};
};