| /* SPDX-License-Identifier: GPL-2.0-only */ | |
| /* | |
| * Copyright (c) 2015 MediaTek Inc. | |
| * Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com> | |
| */ | |
| #ifndef __MFD_MT6328_CORE_H__ | |
| #define __MFD_MT6328_CORE_H__ | |
| enum mt6328_irq_status_numbers { | |
| MT6328_IRQ_STATUS_PWRKEY = 0, | |
| MT6328_IRQ_STATUS_HOMEKEY, | |
| MT6328_IRQ_STATUS_PWRKEY_R, | |
| MT6328_IRQ_STATUS_HOMEKEY_R, | |
| MT6328_IRQ_STATUS_THR_H, | |
| MT6328_IRQ_STATUS_THR_L, | |
| MT6328_IRQ_STATUS_BAT_H, | |
| MT6328_IRQ_STATUS_BAT_L, | |
| MT6328_IRQ_STATUS_RTC, | |
| MT6328_IRQ_STATUS_AUDIO, | |
| MT6328_IRQ_STATUS_ACCDET, | |
| MT6328_IRQ_STATUS_ACCDET_EINT, | |
| MT6328_IRQ_STATUS_ACCDET_NEGV, | |
| MT6328_IRQ_STATUS_NI_LBAT_INT, | |
| MT6328_IRQ_STATUS_VPROC_OC = 16, | |
| MT6328_IRQ_STATUS_VSYS_OC, | |
| MT6328_IRQ_STATUS_VLTE_OC, | |
| MT6328_IRQ_STATUS_VCORE_OC, | |
| MT6328_IRQ_STATUS_VPA_OC, | |
| MT6328_IRQ_STATUS_LDO_OC, | |
| MT6328_IRQ_STATUS_BAT2_H, | |
| MT6328_IRQ_STATUS_BAT2_L, | |
| MT6328_IRQ_STATUS_VISMPS0_H, | |
| MT6328_IRQ_STATUS_VISMPS0_L, | |
| MT6328_IRQ_STATUS_AUXADC_IMP, | |
| MT6328_IRQ_STATUS_OV = 32, | |
| MT6328_IRQ_STATUS_BVALID_DET, | |
| MT6328_IRQ_STATUS_VBATON_HV, | |
| MT6328_IRQ_STATUS_VBATON_UNDET, | |
| MT6328_IRQ_STATUS_WATCHDOG, | |
| MT6328_IRQ_STATUS_PCHR_CM_VDEC, | |
| MT6328_IRQ_STATUS_CHRDET, | |
| MT6328_IRQ_STATUS_PCHR_CM_VINC, | |
| MT6328_IRQ_STATUS_FG_BAT_H, | |
| MT6328_IRQ_STATUS_FG_BAT_L, | |
| MT6328_IRQ_STATUS_FG_CUR_H, | |
| MT6328_IRQ_STATUS_FG_CUR_L, | |
| MT6328_IRQ_STATUS_FG_ZCV, | |
| MT6328_IRQ_STATUS_SPKL_D, | |
| MT6328_IRQ_STATUS_SPKL_AB, | |
| }; | |
| #endif /* __MFD_MT6323_CORE_H__ */ |