| // SPDX-License-Identifier: GPL-2.0 | 
 | /* | 
 |  * Copyright (c) 2015 MediaTek Inc. | 
 |  * Author: Mars.C <mars.cheng@mediatek.com> | 
 |  * | 
 |  */ | 
 |  | 
 | #include <dt-bindings/interrupt-controller/irq.h> | 
 | #include <dt-bindings/interrupt-controller/arm-gic.h> | 
 |  | 
 | / { | 
 | 	compatible = "mediatek,mt6580"; | 
 | 	#address-cells = <1>; | 
 | 	#size-cells = <1>; | 
 | 	interrupt-parent = <&sysirq>; | 
 |  | 
 | 	cpus { | 
 | 		#address-cells = <1>; | 
 | 		#size-cells = <0>; | 
 |  | 
 | 		cpu@0 { | 
 | 			device_type = "cpu"; | 
 | 			compatible = "arm,cortex-a7"; | 
 | 			reg = <0x0>; | 
 | 		}; | 
 | 		cpu@1 { | 
 | 			device_type = "cpu"; | 
 | 			compatible = "arm,cortex-a7"; | 
 | 			reg = <0x1>; | 
 | 		}; | 
 | 		cpu@2 { | 
 | 			device_type = "cpu"; | 
 | 			compatible = "arm,cortex-a7"; | 
 | 			reg = <0x2>; | 
 | 		}; | 
 | 		cpu@3 { | 
 | 			device_type = "cpu"; | 
 | 			compatible = "arm,cortex-a7"; | 
 | 			reg = <0x3>; | 
 | 		}; | 
 |  | 
 | 	}; | 
 |  | 
 | 	system_clk: dummy13m { | 
 | 		compatible = "fixed-clock"; | 
 | 		clock-frequency = <13000000>; | 
 | 		#clock-cells = <0>; | 
 | 	}; | 
 |  | 
 | 	rtc_clk: dummy32k { | 
 | 		compatible = "fixed-clock"; | 
 | 		clock-frequency = <32000>; | 
 | 		#clock-cells = <0>; | 
 | 	}; | 
 |  | 
 | 	uart_clk: dummy26m { | 
 | 		compatible = "fixed-clock"; | 
 | 		clock-frequency = <26000000>; | 
 | 		#clock-cells = <0>; | 
 | 	}; | 
 |  | 
 | 	timer: timer@10008000 { | 
 | 		compatible = "mediatek,mt6580-timer", | 
 | 			     "mediatek,mt6577-timer"; | 
 | 		reg = <0x10008000 0x80>; | 
 | 		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; | 
 | 		clocks = <&system_clk>, <&rtc_clk>; | 
 | 		clock-names = "system-clk", "rtc-clk"; | 
 | 	}; | 
 |  | 
 | 	sysirq: interrupt-controller@10200100 { | 
 | 		compatible = "mediatek,mt6580-sysirq", | 
 | 			     "mediatek,mt6577-sysirq"; | 
 | 		interrupt-controller; | 
 | 		#interrupt-cells = <3>; | 
 | 		interrupt-parent = <&gic>; | 
 | 		reg = <0x10200100 0x1c>; | 
 | 	}; | 
 |  | 
 | 	gic: interrupt-controller@10211000 { | 
 | 		compatible = "arm,cortex-a7-gic"; | 
 | 		interrupt-controller; | 
 | 		#interrupt-cells = <3>; | 
 | 		interrupt-parent = <&gic>; | 
 | 		reg = <0x10211000 0x1000>, | 
 | 		      <0x10212000 0x2000>, | 
 | 		      <0x10214000 0x2000>, | 
 | 		      <0x10216000 0x2000>; | 
 | 	}; | 
 |  | 
 | 	uart0: serial@11005000 { | 
 | 		compatible = "mediatek,mt6580-uart", | 
 | 			     "mediatek,mt6577-uart"; | 
 | 		reg = <0x11005000 0x400>; | 
 | 		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; | 
 | 		clocks = <&uart_clk>; | 
 | 		status = "disabled"; | 
 | 	}; | 
 |  | 
 | 	uart1: serial@11006000 { | 
 | 		compatible = "mediatek,mt6580-uart", | 
 | 			     "mediatek,mt6577-uart"; | 
 | 		reg = <0x11006000 0x400>; | 
 | 		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; | 
 | 		clocks = <&uart_clk>; | 
 | 		status = "disabled"; | 
 | 	}; | 
 | }; |