| /* SPDX-License-Identifier: GPL-2.0 */ | 
 | #ifndef _ASM_X86_MICROCODE_INTEL_H | 
 | #define _ASM_X86_MICROCODE_INTEL_H | 
 |  | 
 | #include <asm/microcode.h> | 
 |  | 
 | struct microcode_header_intel { | 
 | 	unsigned int            hdrver; | 
 | 	unsigned int            rev; | 
 | 	unsigned int            date; | 
 | 	unsigned int            sig; | 
 | 	unsigned int            cksum; | 
 | 	unsigned int            ldrver; | 
 | 	unsigned int            pf; | 
 | 	unsigned int            datasize; | 
 | 	unsigned int            totalsize; | 
 | 	unsigned int            reserved[3]; | 
 | }; | 
 |  | 
 | struct microcode_intel { | 
 | 	struct microcode_header_intel hdr; | 
 | 	unsigned int            bits[0]; | 
 | }; | 
 |  | 
 | /* microcode format is extended from prescott processors */ | 
 | struct extended_signature { | 
 | 	unsigned int            sig; | 
 | 	unsigned int            pf; | 
 | 	unsigned int            cksum; | 
 | }; | 
 |  | 
 | struct extended_sigtable { | 
 | 	unsigned int            count; | 
 | 	unsigned int            cksum; | 
 | 	unsigned int            reserved[3]; | 
 | 	struct extended_signature sigs[0]; | 
 | }; | 
 |  | 
 | #define DEFAULT_UCODE_DATASIZE	(2000) | 
 | #define MC_HEADER_SIZE		(sizeof(struct microcode_header_intel)) | 
 | #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE) | 
 | #define EXT_HEADER_SIZE		(sizeof(struct extended_sigtable)) | 
 | #define EXT_SIGNATURE_SIZE	(sizeof(struct extended_signature)) | 
 |  | 
 | #define get_totalsize(mc) \ | 
 | 	(((struct microcode_intel *)mc)->hdr.datasize ? \ | 
 | 	 ((struct microcode_intel *)mc)->hdr.totalsize : \ | 
 | 	 DEFAULT_UCODE_TOTALSIZE) | 
 |  | 
 | #define get_datasize(mc) \ | 
 | 	(((struct microcode_intel *)mc)->hdr.datasize ? \ | 
 | 	 ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE) | 
 |  | 
 | #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) | 
 |  | 
 | static inline u32 intel_get_microcode_revision(void) | 
 | { | 
 | 	u32 rev, dummy; | 
 |  | 
 | 	native_wrmsrl(MSR_IA32_UCODE_REV, 0); | 
 |  | 
 | 	/* As documented in the SDM: Do a CPUID 1 here */ | 
 | 	native_cpuid_eax(1); | 
 |  | 
 | 	/* get the current revision from MSR 0x8B */ | 
 | 	native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); | 
 |  | 
 | 	return rev; | 
 | } | 
 |  | 
 | #ifdef CONFIG_MICROCODE_INTEL | 
 | extern void __init load_ucode_intel_bsp(void); | 
 | extern void load_ucode_intel_ap(void); | 
 | extern void show_ucode_info_early(void); | 
 | extern int __init save_microcode_in_initrd_intel(void); | 
 | void reload_ucode_intel(void); | 
 | #else | 
 | static inline __init void load_ucode_intel_bsp(void) {} | 
 | static inline void load_ucode_intel_ap(void) {} | 
 | static inline void show_ucode_info_early(void) {} | 
 | static inline int __init save_microcode_in_initrd_intel(void) { return -EINVAL; } | 
 | static inline void reload_ucode_intel(void) {} | 
 | #endif | 
 |  | 
 | #endif /* _ASM_X86_MICROCODE_INTEL_H */ |