arch/powerpc/boot/dts/fsl/p1025rdb.dtsi - third_party/kernel - Git at Google

 /*
  * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
  *
  * Copyright 2011 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
  *     * Neither the name of Freescale Semiconductor nor the
  *       names of its contributors may be used to endorse or promote products
  *       derived from this software without specific prior written permission.
  *
  *
  * ALTERNATIVELY, this software may be distributed under the terms of the
  * GNU General Public License ("GPL") as published by the Free Software
  * Foundation, either version 2 of that License or (at your option) any
  * later version.
  *
  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

 &lbc {
 	nor@0,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "cfi-flash";
 		reg = <0x0 0x0 0x1000000>;
 		bank-width = <2>;
 		device-width = <1>;

 		partition@0 {
 			/* This location must not be altered  */
 			/* 256KB for Vitesse 7385 Switch firmware */
 			reg = <0x0 0x00040000>;
 			label = "NOR Vitesse-7385 Firmware";
 			read-only;
 		};

 		partition@40000 {
 			/* 256KB for DTB Image */
 			reg = <0x00040000 0x00040000>;
 			label = "NOR DTB Image";
 		};

 		partition@80000 {
 			/* 3.5 MB for Linux Kernel Image */
 			reg = <0x00080000 0x00380000>;
 			label = "NOR Linux Kernel Image";
 		};

 		partition@400000 {
 			/* 11MB for JFFS2 based Root file System */
 			reg = <0x00400000 0x00b00000>;
 			label = "NOR JFFS2 Root File System";
 		};

 		partition@f00000 {
 			/* This location must not be altered  */
 			/* 512KB for u-boot Bootloader Image */
 			/* 512KB for u-boot Environment Variables */
 			reg = <0x00f00000 0x00100000>;
 			label = "NOR U-Boot Image";
 			read-only;
 		};
 	};

 	nand@1,0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "fsl,p1025-fcm-nand",
 			     "fsl,elbc-fcm-nand";
 		reg = <0x1 0x0 0x40000>;

 		partition@0 {
 			/* This location must not be altered  */
 			/* 1MB for u-boot Bootloader Image */
 			reg = <0x0 0x00100000>;
 			label = "NAND U-Boot Image";
 			read-only;
 		};

 		partition@100000 {
 			/* 1MB for DTB Image */
 			reg = <0x00100000 0x00100000>;
 			label = "NAND DTB Image";
 		};

 		partition@200000 {
 			/* 4MB for Linux Kernel Image */
 			reg = <0x00200000 0x00400000>;
 			label = "NAND Linux Kernel Image";
 		};

 		partition@600000 {
 			/* 4MB for Compressed Root file System Image */
 			reg = <0x00600000 0x00400000>;
 			label = "NAND Compressed RFS Image";
 		};

 		partition@a00000 {
 			/* 7MB for JFFS2 based Root file System */
 			reg = <0x00a00000 0x00700000>;
 			label = "NAND JFFS2 Root File System";
 		};

 		partition@1100000 {
 			/* 15MB for JFFS2 based Root file System */
 			reg = <0x01100000 0x00f00000>;
 			label = "NAND Writable User area";
 		};
 	};

 };

 &soc {
 	i2c@3000 {
 		rtc@68 {
 			compatible = "dallas,ds1339";
 			reg = <0x68>;
 		};
 	};

 	spi@7000 {
 		flash@0 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "spansion,s25sl12801", "jedec,spi-nor";
 			reg = <0>;
 			spi-max-frequency = <40000000>; /* input clock */

 			partition@u-boot {
 				/* 512KB for u-boot Bootloader Image */
 				reg = <0x0 0x00080000>;
 				label = "u-boot";
 				read-only;
 			};

 			partition@dtb {
 				/* 512KB for DTB Image */
 				reg = <0x00080000 0x00080000>;
 				label = "dtb";
 			};

 			partition@kernel {
 				/* 4MB for Linux Kernel Image */
 				reg = <0x00100000 0x00400000>;
 				label = "kernel";
 			};

 			partition@fs {
 				/* 4MB for Compressed RFS Image */
 				reg = <0x00500000 0x00400000>;
 				label = "file system";
 			};

 			partition@jffs-fs {
 				/* 7MB for JFFS2 based RFS */
 				reg = <0x00900000 0x00700000>;
 				label = "file system jffs2";
 			};
 		};
 	};

 	usb@22000 {
 		phy_type = "ulpi";
 	};

 	/* USB2 is shared with localbus, so it must be disabled
 	   by default. We can't put 'status = "disabled";' here
 	   since U-Boot doesn't clear the status property when
 	   it enables USB2. OTOH, U-Boot does create a new node
 	   when there isn't any. So, just comment it out.
 	usb@23000 {
 		phy_type = "ulpi";
 	};
 	*/

 	mdio@24000 {
 		phy0: ethernet-phy@0 {
 			interrupt-parent = <&mpic>;
 			interrupts = <3 1>;
 			reg = <0x0>;
 		};

 		phy1: ethernet-phy@1 {
 			interrupt-parent = <&mpic>;
 			interrupts = <2 1>;
 			reg = <0x1>;
 		};

 		tbi0: tbi-phy@11 {
 			reg = <0x11>;
 			device_type = "tbi-phy";
 		};
 	};

 	mdio@25000 {
 		tbi1: tbi-phy@11 {
 			reg = <0x11>;
 			device_type = "tbi-phy";
 		};
 	};

 	mdio@26000 {
 		tbi2: tbi-phy@11 {
 			reg = <0x11>;
 			device_type = "tbi-phy";
 		};
 	};

 	enet0: ethernet@b0000 {
 		fixed-link = <1 1 1000 0 0>;
 		phy-connection-type = "rgmii-id";

 	};

 	enet1: ethernet@b1000 {
 		phy-handle = <&phy0>;
 		tbi-handle = <&tbi1>;
 		phy-connection-type = "sgmii";
 	};

 	enet2: ethernet@b2000 {
 		phy-handle = <&phy1>;
 		phy-connection-type = "rgmii-id";
 	};

 	par_io@e0100 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		reg = <0xe0100 0x60>;
 		ranges = <0x0 0xe0100 0x60>;
 		device_type = "par_io";
 		num-ports = <3>;
 		pio1: ucc_pin@1 {
 			pio-map = <
 		/* port  pin  dir  open_drain  assignment  has_irq */
 				0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 				0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
 				0x0  0x17 0x2  0x0  0x2  0x0    /* CLK12 */
 				0x0  0x18 0x2  0x0  0x1  0x0    /* CLK9 */
 				0x0  0x7  0x1  0x0  0x2  0x0    /* ENET1_TXD0_SER1_TXD0 */
 				0x0  0x9  0x1  0x0  0x2  0x0    /* ENET1_TXD1_SER1_TXD1 */
 				0x0  0xb  0x1  0x0  0x2  0x0    /* ENET1_TXD2_SER1_TXD2 */
 				0x0  0xc  0x1  0x0  0x2  0x0    /* ENET1_TXD3_SER1_TXD3 */
 				0x0  0x6  0x2  0x0  0x2  0x0    /* ENET1_RXD0_SER1_RXD0 */
 				0x0  0xa  0x2  0x0  0x2  0x0    /* ENET1_RXD1_SER1_RXD1 */
 				0x0  0xe  0x2  0x0  0x2  0x0    /* ENET1_RXD2_SER1_RXD2 */
 				0x0  0xf  0x2  0x0  0x2  0x0    /* ENET1_RXD3_SER1_RXD3 */
 				0x0  0x5  0x1  0x0  0x2  0x0    /* ENET1_TX_EN_SER1_RTS_B */
 				0x0  0xd  0x1  0x0  0x2  0x0    /* ENET1_TX_ER */
 				0x0  0x4  0x2  0x0  0x2  0x0    /* ENET1_RX_DV_SER1_CTS_B */
 				0x0  0x8  0x2  0x0  0x2  0x0    /* ENET1_RX_ER_SER1_CD_B */
 				0x0  0x11 0x2  0x0  0x2  0x0    /* ENET1_CRS */
 				0x0  0x10 0x2  0x0  0x2  0x0>;    /* ENET1_COL */
 		};

 		pio2: ucc_pin@2 {
 			pio-map = <
 		/* port  pin  dir  open_drain  assignment  has_irq */
 				0x1  0x13 0x1  0x0  0x1  0x0    /* QE_MUX_MDC */
 				0x1  0x14 0x3  0x0  0x1  0x0    /* QE_MUX_MDIO */
 				0x1  0xb  0x2  0x0  0x1  0x0    /* CLK13 */
 				0x1  0x7  0x1  0x0  0x2  0x0    /* ENET5_TXD0_SER5_TXD0 */
 				0x1  0xa  0x1  0x0  0x2  0x0    /* ENET5_TXD1_SER5_TXD1 */
 				0x1  0x6  0x2  0x0  0x2  0x0    /* ENET5_RXD0_SER5_RXD0 */
 				0x1  0x9  0x2  0x0  0x2  0x0    /* ENET5_RXD1_SER5_RXD1 */
 				0x1  0x5  0x1  0x0  0x2  0x0    /* ENET5_TX_EN_SER5_RTS_B */
 				0x1  0x4  0x2  0x0  0x2  0x0    /* ENET5_RX_DV_SER5_CTS_B */
 				0x1  0x8  0x2  0x0  0x2  0x0>;    /* ENET5_RX_ER_SER5_CD_B */
 		};

 		pio3: ucc_pin@3 {
 			pio-map = <
 		/* port  pin  dir  open_drain  assignment  has_irq */
 				0x0  0x16 0x2  0x0  0x2  0x0    /* SER7_CD_B*/
 				0x0  0x12 0x2  0x0  0x2  0x0    /* SER7_CTS_B*/
 				0x0  0x13 0x1  0x0  0x2  0x0    /* SER7_RTS_B*/
 				0x0  0x14 0x2  0x0  0x2  0x0    /* SER7_RXD0*/
 				0x0  0x15 0x1  0x0  0x2  0x0>;    /* SER7_TXD0*/
 		};

 		pio4: ucc_pin@4 {
 			pio-map = <
 		/* port  pin  dir  open_drain  assignment  has_irq */
 				0x1  0x0  0x2  0x0  0x2  0x0    /* SER3_CD_B*/
 				0x0  0x1c 0x2  0x0  0x2  0x0    /* SER3_CTS_B*/
 				0x0  0x1d 0x1  0x0  0x2  0x0    /* SER3_RTS_B*/
 				0x0  0x1e 0x2  0x0  0x2  0x0    /* SER3_RXD0*/
 				0x0  0x1f 0x1  0x0  0x2  0x0>;    /* SER3_TXD0*/
 		};
 	};
 };

 &qe {
 	serial2: ucc@2600 {
 		device_type = "serial";
 		compatible = "ucc_uart";
 		port-number = <0>;
 		rx-clock-name = "brg6";
 		tx-clock-name = "brg6";
 		pio-handle = <&pio3>;
 	};

 	serial3: ucc@2200 {
 		device_type = "serial";
 		compatible = "ucc_uart";
 		port-number = <1>;
 		rx-clock-name = "brg2";
 		tx-clock-name = "brg2";
 		pio-handle = <&pio4>;
 	};
 };
	/*
	* P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
	*
	* Copyright 2011 Freescale Semiconductor Inc.
	*
	* Redistribution and use in source and binary forms, with or without
	* modification, are permitted provided that the following conditions are met:
	* * Redistributions of source code must retain the above copyright
	* notice, this list of conditions and the following disclaimer.
	* * Redistributions in binary form must reproduce the above copyright
	* notice, this list of conditions and the following disclaimer in the
	* documentation and/or other materials provided with the distribution.
	* * Neither the name of Freescale Semiconductor nor the
	* names of its contributors may be used to endorse or promote products
	* derived from this software without specific prior written permission.
	*
	*
	* ALTERNATIVELY, this software may be distributed under the terms of the
	* GNU General Public License ("GPL") as published by the Free Software
	* Foundation, either version 2 of that License or (at your option) any
	* later version.
	*
	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	*/

	&lbc {
	nor@0,0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "cfi-flash";
	reg = <0x0 0x0 0x1000000>;
	bank-width = <2>;
	device-width = <1>;

	partition@0 {
	/* This location must not be altered */
	/* 256KB for Vitesse 7385 Switch firmware */
	reg = <0x0 0x00040000>;
	label = "NOR Vitesse-7385 Firmware";
	read-only;
	};

	partition@40000 {
	/* 256KB for DTB Image */
	reg = <0x00040000 0x00040000>;
	label = "NOR DTB Image";
	};

	partition@80000 {
	/* 3.5 MB for Linux Kernel Image */
	reg = <0x00080000 0x00380000>;
	label = "NOR Linux Kernel Image";
	};

	partition@400000 {
	/* 11MB for JFFS2 based Root file System */
	reg = <0x00400000 0x00b00000>;
	label = "NOR JFFS2 Root File System";
	};

	partition@f00000 {
	/* This location must not be altered */
	/* 512KB for u-boot Bootloader Image */
	/* 512KB for u-boot Environment Variables */
	reg = <0x00f00000 0x00100000>;
	label = "NOR U-Boot Image";
	read-only;
	};
	};

	nand@1,0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,p1025-fcm-nand",
	"fsl,elbc-fcm-nand";
	reg = <0x1 0x0 0x40000>;

	partition@0 {
	/* This location must not be altered */
	/* 1MB for u-boot Bootloader Image */
	reg = <0x0 0x00100000>;
	label = "NAND U-Boot Image";
	read-only;
	};

	partition@100000 {
	/* 1MB for DTB Image */
	reg = <0x00100000 0x00100000>;
	label = "NAND DTB Image";
	};

	partition@200000 {
	/* 4MB for Linux Kernel Image */
	reg = <0x00200000 0x00400000>;
	label = "NAND Linux Kernel Image";
	};

	partition@600000 {
	/* 4MB for Compressed Root file System Image */
	reg = <0x00600000 0x00400000>;
	label = "NAND Compressed RFS Image";
	};

	partition@a00000 {
	/* 7MB for JFFS2 based Root file System */
	reg = <0x00a00000 0x00700000>;
	label = "NAND JFFS2 Root File System";
	};

	partition@1100000 {
	/* 15MB for JFFS2 based Root file System */
	reg = <0x01100000 0x00f00000>;
	label = "NAND Writable User area";
	};
	};

	};

	&soc {
	i2c@3000 {
	rtc@68 {
	compatible = "dallas,ds1339";
	reg = <0x68>;
	};
	};

	spi@7000 {
	flash@0 {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "spansion,s25sl12801", "jedec,spi-nor";
	reg = <0>;
	spi-max-frequency = <40000000>; /* input clock */

	partition@u-boot {
	/* 512KB for u-boot Bootloader Image */
	reg = <0x0 0x00080000>;
	label = "u-boot";
	read-only;
	};

	partition@dtb {
	/* 512KB for DTB Image */
	reg = <0x00080000 0x00080000>;
	label = "dtb";
	};

	partition@kernel {
	/* 4MB for Linux Kernel Image */
	reg = <0x00100000 0x00400000>;
	label = "kernel";
	};

	partition@fs {
	/* 4MB for Compressed RFS Image */
	reg = <0x00500000 0x00400000>;
	label = "file system";
	};

	partition@jffs-fs {
	/* 7MB for JFFS2 based RFS */
	reg = <0x00900000 0x00700000>;
	label = "file system jffs2";
	};
	};
	};

	usb@22000 {
	phy_type = "ulpi";
	};

	/* USB2 is shared with localbus, so it must be disabled
	by default. We can't put 'status = "disabled";' here
	since U-Boot doesn't clear the status property when
	it enables USB2. OTOH, U-Boot does create a new node
	when there isn't any. So, just comment it out.
	usb@23000 {
	phy_type = "ulpi";
	};
	*/

	mdio@24000 {
	phy0: ethernet-phy@0 {
	interrupt-parent = <&mpic>;
	interrupts = <3 1>;
	reg = <0x0>;
	};

	phy1: ethernet-phy@1 {
	interrupt-parent = <&mpic>;
	interrupts = <2 1>;
	reg = <0x1>;
	};

	tbi0: tbi-phy@11 {
	reg = <0x11>;
	device_type = "tbi-phy";
	};
	};

	mdio@25000 {
	tbi1: tbi-phy@11 {
	reg = <0x11>;
	device_type = "tbi-phy";
	};
	};

	mdio@26000 {
	tbi2: tbi-phy@11 {
	reg = <0x11>;
	device_type = "tbi-phy";
	};
	};

	enet0: ethernet@b0000 {
	fixed-link = <1 1 1000 0 0>;
	phy-connection-type = "rgmii-id";

	};

	enet1: ethernet@b1000 {
	phy-handle = <&phy0>;
	tbi-handle = <&tbi1>;
	phy-connection-type = "sgmii";
	};

	enet2: ethernet@b2000 {
	phy-handle = <&phy1>;
	phy-connection-type = "rgmii-id";
	};

	par_io@e0100 {
	#address-cells = <1>;
	#size-cells = <1>;
	reg = <0xe0100 0x60>;
	ranges = <0x0 0xe0100 0x60>;
	device_type = "par_io";
	num-ports = <3>;
	pio1: ucc_pin@1 {
	pio-map = <
	/* port pin dir open_drain assignment has_irq */
	0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
	0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
	0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
	0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
	0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
	0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
	0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
	0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
	0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
	0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
	0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
	0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
	0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
	0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
	0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
	0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
	0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
	0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
	};

	pio2: ucc_pin@2 {
	pio-map = <
	/* port pin dir open_drain assignment has_irq */
	0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
	0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
	0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
	0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
	0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
	0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
	0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
	0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
	0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
	0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
	};

	pio3: ucc_pin@3 {
	pio-map = <
	/* port pin dir open_drain assignment has_irq */
	0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
	0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
	0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
	0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
	0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
	};

	pio4: ucc_pin@4 {
	pio-map = <
	/* port pin dir open_drain assignment has_irq */
	0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
	0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
	0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
	0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
	0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
	};
	};
	};

	&qe {
	serial2: ucc@2600 {
	device_type = "serial";
	compatible = "ucc_uart";
	port-number = <0>;
	rx-clock-name = "brg6";
	tx-clock-name = "brg6";
	pio-handle = <&pio3>;
	};

	serial3: ucc@2200 {
	device_type = "serial";
	compatible = "ucc_uart";
	port-number = <1>;
	rx-clock-name = "brg2";
	tx-clock-name = "brg2";
	pio-handle = <&pio4>;
	};
	};