| /* |
| * Copyright 2021 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: AMD |
| * |
| */ |
| |
| #ifndef __DCN32_CLK_MGR_SMU_MSG_H_ |
| #define __DCN32_CLK_MGR_SMU_MSG_H_ |
| |
| #include "core_types.h" |
| #include "dcn30/dcn30_clk_mgr_smu_msg.h" |
| |
| #define FCLK_PSTATE_NOTSUPPORTED 0x00 |
| #define FCLK_PSTATE_SUPPORTED 0x01 |
| |
| /* TODO Remove this MSG ID define after it becomes available in dalsmc */ |
| #define DALSMC_MSG_SetCabForUclkPstate 0x12 |
| #define DALSMC_Result_OK 0x1 |
| |
| void |
| dcn32_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool enable); |
| void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); |
| void dcn32_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr); |
| void dcn32_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways); |
| void dcn32_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); |
| unsigned int dcn32_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz); |
| |
| #endif /* __DCN32_CLK_MGR_SMU_MSG_H_ */ |