| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for J721E SoC Family |
| * |
| * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/pinctrl/k3.h> |
| #include <dt-bindings/soc/ti,sci_pm_domain.h> |
| |
| / { |
| model = "Texas Instruments K3 J721E SoC"; |
| compatible = "ti,j721e"; |
| interrupt-parent = <&gic500>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| serial0 = &wkup_uart0; |
| serial1 = &mcu_uart0; |
| serial2 = &main_uart0; |
| serial3 = &main_uart1; |
| serial4 = &main_uart2; |
| serial5 = &main_uart3; |
| serial6 = &main_uart4; |
| serial7 = &main_uart5; |
| serial8 = &main_uart6; |
| serial9 = &main_uart7; |
| serial10 = &main_uart8; |
| serial11 = &main_uart9; |
| }; |
| |
| chosen { }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu-map { |
| cluster0: cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| }; |
| |
| }; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x000>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xC000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x001>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xC000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&L2_0>; |
| }; |
| }; |
| |
| L2_0: l2-cache0 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-size = <0x100000>; |
| cache-line-size = <64>; |
| cache-sets = <2048>; |
| next-level-cache = <&msmc_l3>; |
| }; |
| |
| msmc_l3: l3-cache0 { |
| compatible = "cache"; |
| cache-level = <3>; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| |
| psci: psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| }; |
| |
| a72_timer0: timer-cl0-cpu0 { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ |
| }; |
| |
| pmu: pmu { |
| compatible = "arm,armv8-pmuv3"; |
| /* Recommendation from GIC500 TRM Table A.3 */ |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| cbass_main: interconnect@100000 { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ |
| <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ |
| <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ |
| <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */ |
| <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ |
| <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ |
| <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ |
| <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ |
| <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ |
| <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ |
| <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */ |
| <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ |
| <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ |
| |
| /* MCUSS_WKUP Range */ |
| <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, |
| <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, |
| <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, |
| <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, |
| <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, |
| <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, |
| <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, |
| <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, |
| <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, |
| <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, |
| <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, |
| <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, |
| <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; |
| |
| cbass_mcu_wakeup: interconnect@28380000 { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ |
| <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ |
| <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ |
| <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ |
| <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ |
| <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ |
| <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ |
| <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ |
| <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ |
| <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ |
| <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ |
| <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ |
| <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ |
| }; |
| }; |
| }; |
| |
| /* Now include the peripherals for each bus segments */ |
| #include "k3-j721e-main.dtsi" |
| #include "k3-j721e-mcu-wakeup.dtsi" |