cros/dts/flashmap-x86-ro.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Flash layout for x86 (for testing purposes only)
 *
 * Copyright 2018 Google LLC
 */

#include <config.h>

/ {
	binman {
		chromeos: image {
		};
	};
};

#define RO_BASE		0xff000000

&chromeos {
	filename = "image.bin";
	u-boot,dm-spl;
	u-boot,dm-vpl;
	end-at-4gb;
	sort-by-offset;
	pad-byte = <0xff>;
	size = <CONFIG_ROM_SIZE>;
	compatible = "chromeos,flashmap";
	/* ---- Section: Vital-product data (VPD) ---- */
	read-only-vpd {
		offset = <0xff800000>;
		type = "section";
		label-prefix = "ro-";
		read-only;
		align-size = <0x10000>;
		vpd {
			size = <0x4000>;
			type = "fill";
			fill-value = [ff];
		};
	};
	fdtmap {
	};
	read-only {
		u-boot,dm-spl;
		u-boot,dm-vpl;
		type = "section";
		label-prefix = "ro-";
		sort-by-offset;
		read-only;
		offset = <0xff000000>;
#if defined(CONFIG_HAVE_INTEL_ME) || defined(CONFIG_FSP_VERSION2)
		intel-descriptor {
			filename = CONFIG_FLASH_DESCRIPTOR_FILE;
		};
#endif
#ifdef CONFIG_FSP_VERSION2
		intel-ifwi {
			filename = CONFIG_IFWI_INPUT_FILE;
			convert-fit;

			section {
				size = <0x8000>;
				ifwi-replace;
				ifwi-subpart = "IBBP";
				ifwi-entry = "IBBL";
				tpl {
					type = "u-boot-tpl";
				};
				x86-start16-tpl {
					offset = <0x7800>;
				};
				x86-reset16-tpl {
					offset = <0x7ff0>;
				};
			};
		};
#endif
#ifdef CONFIG_HAVE_INTEL_ME
		intel-me {
			filename = CONFIG_INTEL_ME_FILE;
		};
#endif
		vpl {
			type = "section";
			u-boot-vpl-nodtb {
				spl-pad;
			};
			u-boot-vpl-dtb {
			};
		};
		fmap {
			offset = <(0xff200000 - RO_BASE)>;
			size = <0x1200>;
		};
		firmware-id {
			u-boot,dm-vpl;
			size = <0x40>;
			type = "text";
			text-label = "frid";
		};

		gbb {
			type = "gbb";
			u-boot,dm-vpl;
			size = <0x3000>;
			expand-size;
			align = <0x1000>;
		};
		locales {
			compatible = "chromeos,locales";
			type = "files";
			pattern = "locales/*";
			require-matches;
			files-compress = "lz4";
			align = <0x40>;

			/* Intel SPI flash driver requires word alignment */
			files-align = <4>;
		};
		boot-rec {
			align = <0x1000>;
			u-boot,dm-vpl;
			type = "u-boot";
			hash {
				u-boot,dm-vpl;
				algo = "sha256";
			};
		};
		u-boot-dtb {
		};
		u-boot-ucode {
		};

#ifdef CONFIG_HAVE_MICROCODE
		u-boot-tpl-with-ucode-ptr {
			offset = <(CONFIG_TPL_TEXT_BASE - RO_BASE)>;
		};
		u-boot-tpl-dtb-with-ucode {
		};
#endif
#ifdef CONFIG_FSP_VERSION2
		intel-fsp-m {
			filename = CONFIG_FSP_FILE_M;
		};
		intel-fsp-s {
			filename = CONFIG_FSP_FILE_S;
		};
#ifdef CONFIG_HAVE_VBT
		intel-vbt {
			filename = CONFIG_VBT_FILE;
		};
#endif
#endif
		u-boot-spl-rec {
			u-boot,dm-vpl;
			type = "u-boot-spl";
		};
		spl {
			type = "section";
			u-boot-spl {
			};
			u-boot-spl-dtb {
			};
		};
#ifdef CONFIG_HAVE_MRC
		intel-mrc {
			offset = <(CONFIG_X86_MRC_ADDR - RO_BASE)>;
		};
#endif
#ifdef CONFIG_HAVE_VGA_BIOS
		intel-vga {
			filename = CONFIG_VGA_BIOS_FILE;
			offset = <(CONFIG_VGA_BIOS_ADDR - RO_BASE)>;
		};
#endif
#ifdef CONFIG_HAVE_REFCODE
		intel-refcode {
			offset = <(CONFIG_X86_REFCODE_ADDR - RO_BASE)>;
		};
#endif
#ifndef CONFIG_FSP_VERSION2
#ifdef CONFIG_TPL
		x86-start16-tpl {
			offset = <(CONFIG_SYS_X86_START16 - RO_BASE)>;
		};
		x86-reset16-tpl {
			offset = <(CONFIG_RESET_VEC_LOC - RO_BASE)>;
		};
#elif defined(CONFIG_SPL)
		x86-start16-spl {
			offset = <(CONFIG_SYS_X86_START16 - RO_BASE)>;
		};
		x86-reset16-spl {
			offset = <(CONFIG_RESET_VEC_LOC - RO_BASE)>;
		};
#else
		x86-start16 {
			offset = <(CONFIG_SYS_X86_START16 - RO_BASE)>;
		};
		x86-reset16 {
			offset = <(CONFIG_RESET_VEC_LOC - RO_BASE)>;
		};
#endif
#endif
	};
};