cros/dts/flashmap-16mb-x86-rw.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Read/write flash map for a 16MB SPI flash
 *
 * Copyright 2018 Google LLC
 */

&chromeos {
	/*
	 * Note: rw-a and rw-b are used by auto-update. They must be
	 * the same size, and must include the vblock, boot and
	 * firmware-id parts within them. There is no check on this
	 * at present so you need to manually verify that it is
	 * correct.
	 *
	 * The rw-b section must not overlap/include the rw-vpd
	 * section.
	 */

	/* ---- Section: Rewritable slot A ---- */
	read-write-a {
		align = <0x10000>;
		u-boot,dm-vpl;
		type = "section";
		label-prefix = "rw-a-";
		block-offset = /bits/ 64 <0x00004400>;
		vblock {
			align = <0x1000>;
			align-size = <0x1000>;
			u-boot,dm-vpl;
			/*
			 * Alignment: 4k (for updating) and must be in
			 * start of each RW_SECTION
			 */
			size = <0x2000>;
			content = <&rw_a_spl>;
			keyblock = "firmware.keyblock";
			signprivate = "firmware_data_key.vbprivk";
			version = <1>;
			kernelkey = "kernel_subkey.vbpubk";
			preamble-flags = <0>;
		};
		rw_a_spl: u-boot-spl {
			u-boot,dm-vpl;
			align = <4>;
			type = "u-boot-spl";
		};
		u-boot {
			type = "section";
			align = <0x1000>;
			u-boot,dm-vpl;
			/*compress = "lz4";*/
			section {
				u-boot-nodtb {
				};
				u-boot-dtb {
				};
			};
			hash {
				u-boot,dm-vpl;
				algo = "sha256";
			};
		};
		ecrw {
			type = "cros-ec-rw";
			u-boot,dm-vpl;
			align = <4>;
			align-size = <0x1000>;
			hash {
				u-boot,dm-vpl;
				algo = "sha256";
			};
		};
		firmware-id {
			/* Alignment: no requirement */
			u-boot,dm-vpl;
			align = <4>;
			size = <0x100>;
			type = "text";
			text-label = "frid";
		};
		private-files {
			type = "files";
			pattern = "*.dat";
		};
#ifdef CONFIG_HAVE_VBT
		intel-vbt {
			align = <4>;
			filename = CONFIG_VBT_FILE;
		};
#endif
	};

	/* ---- Section: Rewritable slot B ---- */
	read-write-b {
		align = <0x10000>;
		u-boot,dm-vpl;
		type = "section";
		label-prefix = "rw-b-";
		block-offset = /bits/ 64 <0x00084400>;

		vblock {
			align = <0x1000>;
			align-size = <0x1000>;
			u-boot,dm-vpl;
			/*
			 * Alignment: 4k (for updating) and must be in
			 * start of each RW_SECTION
			 */
			size = <0x2000>;
			content = <&rw_b_spl>;
			keyblock = "firmware.keyblock";
			signprivate = "firmware_data_key.vbprivk";
			version = <1>;
			kernelkey = "kernel_subkey.vbpubk";
			preamble-flags = <0>;
		};
		rw_b_spl: u-boot-spl {
			u-boot,dm-vpl;
			align = <4>;
			type = "u-boot-spl";
		};
		u-boot {
			type = "section";
			align = <0x1000>;
			u-boot,dm-vpl;
			/*compress = "lz4"; */
			section {
				u-boot-nodtb {
				};
				u-boot-dtb {
				};
				hash {
					u-boot,dm-vpl;
					algo = "sha256";
				};
			};
		};
		ecrw {
			type = "cros-ec-rw";
			u-boot,dm-vpl;
			align = <4>;
			align-size = <0x1000>;
			hash {
				u-boot,dm-vpl;
				algo = "sha256";
			};
		};
		firmware-id {
			/* Alignment: no requirement */
			u-boot,dm-vpl;
			align = <4>;
			size = <0x100>;
			type = "text";
			text-label = "frid";
		};
		private-files {
			type = "files";
			pattern = "*.dat";
		};
#ifdef CONFIG_HAVE_VBT
		intel-vbt {
			filename = CONFIG_VBT_FILE;
		};
#endif
	};

	/* ---- Section: Rewritable VPD 32 KB ---- */
	read-write-vpd {
		type = "section";
		rw-vpd {
			/* Alignment: 4k (for updating) */
			size = <0x00008000>;
			type = "fill";
			fill-value = [ff];
		};
	};

	/* ---- Section: Rewritable shared 16 KB---- */
	shared-section {
		type = "section";
		/* Anything in this range may be updated in recovery */
		size = <0x4000>;
		shared-data {
			label = "shared-data";
			/*
			 * Alignment: 4k (for random read/write).
			 * RW firmware can put calibration data here
			 */
			size = <0x00004000>;
			type = "fill";
			fill-value = [00];
		};
	};

	/* ---- Section: Rewritable private 16 KB---- */
	rw-private {
		type = "section";
		size = <0x00014000>;
		rw-environment {
			label = "rw-environment";
			/*
			 * Alignment: 4k, and must occupy bottom of
			 * U-Boot firmware -- check CONFIG_ENV_OFFSET
			 */
			size = <0x00004000>;

			/*
			 * We could put the dev environment here, but
			 * U-Boot has a default built in. Devs can
			 * 'saveenv' to set this up.
			 */
			type = "fill";
			fill-value = [00];
		};
		recovery-mrc-cache {
			size = <0x10000>;
			type = "fill";
			fill-value = [ff];
		};
	};

	rw-mrc-cache {
		type = "blob";
		offset = <0xff8e0000>;
		size = <0x10000>;
		filename = "board/google/chromebook_coral/rw-mrc-cache";
	};
	rw-var-mrc-cache {
		type = "blob";
		size = <0x1000>;
		filename = "board/google/chromebook_coral/rw-var-mrc-cache";
	};
};