| /* |
| * (C) Copyright 2002 |
| * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| * Marius Groeger <mgroeger@sysgo.de> |
| * Gary Jennejohn <gj@denx.de> |
| * David Mueller <d.mueller@elsoft.ch> |
| * |
| * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board. |
| * |
| * See file CREDITS for list of people who contributed to this |
| * project. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; either version 2 of |
| * the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| * MA 02111-1307 USA |
| */ |
| |
| #ifndef __CONFIG_H |
| #define __CONFIG_H |
| |
| //#define FPGA_SMDKC110 |
| |
| /* |
| * High Level Configuration Options |
| * (easy to change) |
| */ |
| #define CONFIG_S5PC110 1 /* in a SAMSUNG S3C6410 SoC */ |
| #define CONFIG_S5PC11X 1 /* in a SAMSUNG S3C64XX Family */ |
| #define CONFIG_SMDKC110 1 |
| |
| #define CONFIG_MCP_SINGLE 1 |
| #define CONFIG_VOGUES 1 |
| #define CONFIG_EVT1 1 /* EVT1 */ |
| |
| #define BOOT_ONENAND 0x1 |
| #define BOOT_NAND 0x2 |
| #define BOOT_MMCSD 0x3 |
| #define BOOT_NOR 0x4 |
| #define BOOT_SEC_DEV 0x5 |
| |
| /* skip to load BL2 */ |
| //#define FAST_BOOT 1 |
| |
| #define MEMORY_BASE_ADDRESS 0x20000000 |
| |
| /* input clock of PLL */ |
| #define CONFIG_SYS_CLK_FREQ 24000000 /* the SMDK6400 has 24MHz input clock */ |
| |
| #define CONFIG_ENABLE_MMU |
| |
| #ifdef CONFIG_ENABLE_MMU |
| #define virt_to_phys(x) virt_to_phy_smdkc110(x) |
| #else |
| #define virt_to_phys(x) (x) |
| #endif |
| |
| #define CONFIG_MEMORY_UPPER_CODE |
| |
| #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| |
| #define CONFIG_INCLUDE_TEST |
| |
| #define CONFIG_ZIMAGE_BOOT |
| //#define CONFIG_IMAGE_BOOT |
| |
| #define BOARD_LATE_INIT |
| |
| #define CONFIG_SETUP_MEMORY_TAGS |
| #define CONFIG_CMDLINE_TAG |
| #define CONFIG_INITRD_TAG |
| |
| /* |
| * Architecture magic and machine type |
| */ |
| |
| |
| #define MACH_TYPE 2474 |
| |
| #define UBOOT_MAGIC (0x43090000 | MACH_TYPE) |
| |
| /* Power Management is enabled */ |
| #define CONFIG_PM |
| |
| #define CONFIG_DISPLAY_CPUINFO |
| #define CONFIG_DISPLAY_BOARDINFO |
| |
| #undef CONFIG_SKIP_RELOCATE_UBOOT |
| #undef CONFIG_USE_NOR_BOOT |
| |
| /* |
| * Size of malloc() pool |
| */ |
| #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024*1024) |
| #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| |
| #define CONFIG_STACK_SIZE 512*1024 |
| |
| /* |
| * Hardware drivers |
| */ |
| #define CONFIG_DRIVER_DM9000 1 |
| #define DM9000_16BIT_DATA |
| #ifdef CONFIG_DRIVER_DM9000 |
| #define CONFIG_DM9000_BASE (0xA8000000) |
| #define DM9000_IO (CONFIG_DM9000_BASE) |
| #if defined(DM9000_16BIT_DATA) |
| #define DM9000_DATA (CONFIG_DM9000_BASE+2) |
| #else |
| #define DM9000_DATA (CONFIG_DM9000_BASE+1) |
| #endif |
| #endif |
| /* |
| * select serial console configuration |
| */ |
| |
| #define CONFIG_SERIAL3 1 /* we use UART2 on SMDKC110 */ |
| |
| #define CFG_HUSH_PARSER /* use "hush" command parser */ |
| #ifdef CFG_HUSH_PARSER |
| #define CFG_PROMPT_HUSH_PS2 "> " |
| #endif |
| |
| #define CONFIG_CMDLINE_EDITING |
| |
| #undef CONFIG_S3C64XX_I2C /* this board has H/W I2C */ |
| #ifdef CONFIG_S3C64XX_I2C |
| #define CONFIG_HARD_I2C 1 |
| #define CFG_I2C_SPEED 50000 |
| #define CFG_I2C_SLAVE 0xFE |
| #endif |
| |
| #define CONFIG_DOS_PARTITION |
| #define CONFIG_SUPPORT_VFAT |
| |
| #define CONFIG_USB_OHCI |
| #undef CONFIG_USB_STORAGE |
| #define CONFIG_S3C_USBD |
| |
| #define USBD_DOWN_ADDR 0xc0000000 |
| |
| /************************************************************ |
| * RTC |
| ************************************************************/ |
| /* allow to overwrite serial and ethaddr */ |
| #define CONFIG_ENV_OVERWRITE |
| |
| #define CONFIG_BAUDRATE 115200 |
| |
| /*********************************************************** |
| * Command definition |
| ***********************************************************/ |
| #define CONFIG_CMD_CACHE |
| #define CONFIG_CMD_USB |
| #define CONFIG_CMD_REGINFO |
| #define CONFIG_CMD_NET |
| #define CONFIG_NET_MULTI |
| //#define CONFIG_CMD_BMP /* BMP support */ |
| //#define CONFIG_LCD |
| |
| #define CMD_SAVEENV |
| |
| //#define CONFIG_CMD_NAND |
| |
| //#define CONFIG_CMD_IDE |
| //#define CONFIG_CMD_FLASH |
| |
| #ifndef FPGA_SMDKC110 |
| //#define CONFIG_CMD_ONENAND |
| #define CONFIG_CMD_MOVINAND |
| #endif |
| //#define CONFIG_CMD_PING |
| //#define CONFIG_CMD_DATE |
| |
| #include <config_cmd_default.h> |
| |
| #define CONFIG_CMD_ELF |
| //#define CONFIG_CMD_DHCP |
| //#define CONFIG_CMD_I2C |
| |
| /* |
| * BOOTP options |
| */ |
| //#define CONFIG_BOOTP_SUBNETMASK |
| //#define CONFIG_BOOTP_GATEWAY |
| //#define CONFIG_BOOTP_HOSTNAME |
| //#define CONFIG_BOOTP_BOOTPATH |
| |
| /*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ |
| #define CONFIG_ETHADDR 00:40:5c:26:0a:5b |
| #define CONFIG_NETMASK 255.255.255.0 |
| #define CONFIG_IPADDR 192.168.0.20 |
| #define CONFIG_SERVERIP 192.168.0.10 |
| #define CONFIG_GATEWAYIP 192.168.0.1 |
| |
| #define CONFIG_ZERO_BOOTDELAY_CHECK |
| |
| #if defined(CONFIG_CMD_KGDB) |
| #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
| /* what's this ? it's not used anywhere */ |
| #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
| #endif |
| |
| /* |
| * LCD options |
| */ |
| #define CONFIG_S3C_FB |
| #define CONFIG_LCD_HT101HD1 /* LCD type */ |
| |
| #if defined(CONFIG_LCD) |
| #define LCD_BPP LCD_COLOR16 |
| #define CONFIG_SYS_FB_ADDR MEMORY_BASE_ADDRESS + 0x4000000 |
| #endif |
| |
| #if defined(CONFIG_LCD_HT101HD1) |
| #define LCD_WIDTH 1366 |
| #define LCD_HEIGHT 768 |
| #endif |
| |
| /* |
| * Miscellaneous configurable options |
| */ |
| #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| |
| #define CONFIG_SYS_PROMPT "VOGUESV210 # " /* Monitor Command Prompt */ |
| |
| #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ |
| #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| |
| #define CONFIG_SYS_MEMTEST_START MEMORY_BASE_ADDRESS /* memtest works on */ |
| #define CONFIG_SYS_MEMTEST_END MEMORY_BASE_ADDRESS + 0x3FE00000 /* 1024 MB in DRAM */ |
| |
| #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
| |
| #define CONFIG_SYS_LOAD_ADDR MEMORY_BASE_ADDRESS /* default load address */ |
| |
| /* the PWM TImer 4 uses a counter of 41687 for 10 ms, so we need */ |
| /* it to wrap 100 times (total 4168750) to get 1 sec. */ |
| #define CONFIG_SYS_HZ 4168750 // at PCLK 66MHz |
| |
| #define CONFIG_TIMEOUT (5*CONFIG_SYS_HZ) |
| #define CONFIG_ARP_TIMEOUT (5*CONFIG_SYS_HZ) |
| |
| /* valid baudrates */ |
| #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| |
| /*----------------------------------------------------------------------- |
| * Stack sizes |
| * |
| * The stack sizes are set up in start.S using the settings below |
| */ |
| #define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */ |
| #ifdef CONFIG_USE_IRQ |
| #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
| #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
| #endif |
| |
| //#define CONFIG_CLK_667_166_166_133 |
| //#define CONFIG_CLK_533_133_100_100 |
| #define CONFIG_CLK_800_200_166_133 |
| //#define CONFIG_CLK_1000_200_166_133 |
| |
| #if defined(CONFIG_CLK_667_166_166_133) |
| #define APLL_MDIV 0xfa |
| #define APLL_PDIV 0x6 |
| #define APLL_SDIV 0x1 |
| #elif defined(CONFIG_CLK_533_133_100_100) |
| #define APLL_MDIV 0x215 |
| #define APLL_PDIV 0x18 |
| #define APLL_SDIV 0x1 |
| #elif defined(CONFIG_CLK_800_200_166_133) |
| #define APLL_MDIV 0xc8 |
| #define APLL_PDIV 0x6 |
| #define APLL_SDIV 0x1 |
| #elif defined(CONFIG_CLK_1000_200_166_133) |
| #define APLL_MDIV 0xfa |
| #define APLL_PDIV 0x6 |
| #define APLL_SDIV 0x1 |
| #endif |
| |
| #if defined(CONFIG_EVT1) |
| /* Set AFC value */ |
| #define AFC_ON 0x00000000 |
| #define AFC_OFF 0x10000010 |
| #endif |
| |
| #if defined(CONFIG_CLK_533_133_100_100) |
| #define MPLL_MDIV 0x190 |
| #define MPLL_PDIV 0x6 |
| #define MPLL_SDIV 0x2 |
| #else |
| #define MPLL_MDIV 0x29b |
| #define MPLL_PDIV 0xc |
| #define MPLL_SDIV 0x1 |
| #endif |
| |
| #define EPLL_MDIV 0x60 |
| #define EPLL_PDIV 0x6 |
| #define EPLL_SDIV 0x2 |
| |
| #define VPLL_MDIV 0x6c |
| #define VPLL_PDIV 0x6 |
| #define VPLL_SDIV 0x3 |
| |
| /* CLK_DIV0 */ |
| #define APLL_RATIO 0 |
| #define A2M_RATIO 4 |
| #define HCLK_MSYS_RATIO 8 |
| #define PCLK_MSYS_RATIO 12 |
| #define HCLK_DSYS_RATIO 16 |
| #define PCLK_DSYS_RATIO 20 |
| #define HCLK_PSYS_RATIO 24 |
| #define PCLK_PSYS_RATIO 28 |
| |
| #define CLK_DIV0_MASK 0x7fffffff |
| |
| #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) |
| |
| #define APLL_VAL set_pll(APLL_MDIV,APLL_PDIV,APLL_SDIV) |
| #define MPLL_VAL set_pll(MPLL_MDIV,MPLL_PDIV,MPLL_SDIV) |
| #define EPLL_VAL set_pll(EPLL_MDIV,EPLL_PDIV,EPLL_SDIV) |
| #define VPLL_VAL set_pll(VPLL_MDIV,VPLL_PDIV,VPLL_SDIV) |
| |
| #if defined(CONFIG_CLK_667_166_166_133) |
| #define CLK_DIV0_VAL ((0<<APLL_RATIO)|(3<<A2M_RATIO)|(3<<HCLK_MSYS_RATIO)|(1<<PCLK_MSYS_RATIO)\ |
| |(3<<HCLK_DSYS_RATIO)|(1<<PCLK_DSYS_RATIO)|(4<<HCLK_PSYS_RATIO)|(1<<PCLK_PSYS_RATIO)) |
| #elif defined(CONFIG_CLK_533_133_100_100) |
| #define CLK_DIV0_VAL ((0<<APLL_RATIO)|(3<<A2M_RATIO)|(3<<HCLK_MSYS_RATIO)|(1<<PCLK_MSYS_RATIO)\ |
| |(3<<HCLK_DSYS_RATIO)|(1<<PCLK_DSYS_RATIO)|(3<<HCLK_PSYS_RATIO)|(1<<PCLK_PSYS_RATIO)) |
| #elif defined(CONFIG_CLK_800_200_166_133) |
| #define CLK_DIV0_VAL ((0<<APLL_RATIO)|(3<<A2M_RATIO)|(3<<HCLK_MSYS_RATIO)|(1<<PCLK_MSYS_RATIO)\ |
| |(3<<HCLK_DSYS_RATIO)|(1<<PCLK_DSYS_RATIO)|(4<<HCLK_PSYS_RATIO)|(1<<PCLK_PSYS_RATIO)) |
| #elif defined(CONFIG_CLK_1000_200_166_133) |
| #define CLK_DIV0_VAL ((0<<APLL_RATIO)|(4<<A2M_RATIO)|(4<<HCLK_MSYS_RATIO)|(1<<PCLK_MSYS_RATIO)\ |
| |(3<<HCLK_DSYS_RATIO)|(1<<PCLK_DSYS_RATIO)|(4<<HCLK_PSYS_RATIO)|(1<<PCLK_PSYS_RATIO)) |
| #endif |
| |
| #define CLK_DIV1_VAL ((1<<16)|(1<<12)|(1<<8)|(1<<4)) |
| #define CLK_DIV2_VAL (1<<0) |
| |
| #if defined(CONFIG_CLK_533_133_100_100) |
| |
| #if defined(CONFIG_MCP_SINGLE) |
| |
| #define DMC0_TIMINGA_REF 0x40e |
| #define DMC0_TIMING_ROW 0x10233206 |
| #define DMC0_TIMING_DATA 0x12130005 |
| #define DMC0_TIMING_PWR 0x0E100222 |
| |
| #define DMC1_TIMINGA_REF 0x40e |
| #define DMC1_TIMING_ROW 0x10233206 |
| #define DMC1_TIMING_DATA 0x12130005 |
| #define DMC1_TIMING_PWR 0x0E100222 |
| |
| #else |
| |
| #error "You should define memory type (AC type or H type or B type)" |
| |
| #endif |
| |
| #elif defined(CONFIG_CLK_800_200_166_133) || defined(CONFIG_CLK_1000_200_166_133) |
| |
| #if defined(CONFIG_MCP_SINGLE) |
| |
| #define DMC0_MEMCONFIG_0 0x20E01323 // MemConfig0 256MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed |
| #define DMC0_MEMCONFIG_1 0x40F01323 // MemConfig1 |
| #define DMC0_TIMINGA_REF 0x0000040E // TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4E) |
| #define DMC0_TIMING_ROW 0x28233287 // TimingRow for @200MHz |
| #define DMC0_TIMING_DATA 0x23240304 // TimingData CL=3 |
| #define DMC0_TIMING_PWR 0x09C80232 // TimingPower |
| |
| #define DMC1_MEMCONTROL 0x00202400 // MemControl BL=4, 2 chip, DDR2 type, dynamic self refresh, force precharge, dynamic power down off |
| #define DMC1_MEMCONFIG_0 0x40C01323 // MemConfig0 512MB config, 8 banks,Mapping Method[12:15]0:linear, 1:linterleaved, 2:Mixed |
| #define DMC1_MEMCONFIG_1 0x00E01323 // MemConfig1 |
| #define DMC1_TIMINGA_REF 0x0000040E // TimingAref 7.8us*133MHz=1038(0x40E), 100MHz=780(0x30C), 20MHz=156(0x9C), 10MHz=78(0x4 |
| #define DMC1_TIMING_ROW 0x28233289 // TimingRow for @200MHz |
| #define DMC1_TIMING_DATA 0x23240304 // TimingData CL=3 |
| #define DMC1_TIMING_PWR 0x08280232 // TimingPower |
| |
| #else |
| |
| #error "You should define memory type (AC type or H type)" |
| |
| #endif // |
| |
| #else |
| |
| #define DMC0_TIMINGA_REF 0x50e |
| #define DMC0_TIMING_ROW 0x14233287 |
| #define DMC0_TIMING_DATA 0x12130005 |
| #define DMC0_TIMING_PWR 0x0E140222 |
| |
| #define DMC1_TIMINGA_REF 0x618 |
| #define DMC1_TIMING_ROW 0x11344309 |
| #define DMC1_TIMING_DATA 0x12130005 |
| #define DMC1_TIMING_PWR 0x0E190222 |
| |
| #endif |
| |
| |
| #if defined(CONFIG_CLK_533_133_100_100) |
| #define UART_UBRDIV_VAL 26 |
| #define UART_UDIVSLOT_VAL 0x0808 |
| #else |
| #define UART_UBRDIV_VAL 34 |
| #define UART_UDIVSLOT_VAL 0xDDDD |
| #endif |
| |
| #define CONFIG_NR_DRAM_BANKS 1 /* we have 2 bank of DRAM */ |
| #define PHYS_SDRAM_1 MEMORY_BASE_ADDRESS /* SDRAM Bank #1 */ |
| |
| #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ |
| |
| /* |
| * FLASH on the Local Bus |
| */ |
| #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| //#define CONFIG_FLASH_CFI_LEGACY |
| #define CONFIG_SYS_FLASH_BASE 0x80000000 |
| #define CONFIG_SYS_FLASH_SIZE 0x00800000//8 |
| #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| #define CONFIG_SYS_MAX_FLASH_SECT 135 |
| #define CONFIG_SYS_FLASH_PROTECTION 1 |
| |
| /* timeout values are in ticks */ |
| #define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
| #define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
| /*----------------------------------------------------------------------- |
| * FLASH and environment organization |
| */ |
| #if 0 |
| #define CONFIG_MX_LV640EB /* MX29LV640EB */ |
| //#define CONFIG_AMD_LV800 /* AM29LV800BB */ |
| |
| //#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| |
| #if defined(CONFIG_MX_LV640EB) |
| #define CONFIG_SYS_MAX_FLASH_SECT 135 |
| #define PHYS_FLASH_SIZE 0x800000 /* 8MB */ |
| #elif defined(CONFIG_AMD_LV800) |
| #define CONFIG_SYS_MAX_FLASH_SECT 19 |
| #define PHYS_FLASH_SIZE 0x100000 /* 1MB */ |
| #else |
| #define CONFIG_SYS_MAX_FLASH_SECT 512 |
| #define PHYS_FLASH_SIZE 0x100000 /* 1MB */ |
| #endif |
| |
| |
| /* timeout values are in ticks */ |
| |
| #define CFG_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
| CFG_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
| #endif |
| |
| #define CONFIG_ENV_IS_IN_FLASH 1 |
| |
| /* |
| * SMDKC110 board specific data |
| */ |
| #define CONFIG_ENV_OFFSET 0x0070000 |
| #define CONFIG_ENV_SIZE 0x10000 //0x4000 /* Total Size of Environment Sector */ |
| #define CONFIG_ENV_ADDR (CONFIG_ENV_OFFSET+CONFIG_SYS_FLASH_BASE) |
| |
| #define CONFIG_IDENT_STRING " for VOGUESV210" |
| |
| /* total memory required by uboot */ |
| #define CFG_UBOOT_SIZE (2*1024*1024) |
| |
| /* base address for uboot */ |
| #ifdef CONFIG_ENABLE_MMU |
| #define CFG_UBOOT_BASE 0xc3e00000 |
| #else |
| #define CFG_UBOOT_BASE 0x23e00000 |
| #endif |
| |
| #define CFG_PHY_UBOOT_BASE MEMORY_BASE_ADDRESS + 0x3e00000 |
| #define CFG_PHY_KERNEL_BASE MEMORY_BASE_ADDRESS + 0x8000 |
| |
| #define CFG_ENV_OFFSET 0x00070000 |
| |
| /* nand copy size from nand to DRAM.*/ |
| #define COPY_BL2_SIZE 0x80000 |
| |
| /* NAND configuration */ |
| #define CFG_MAX_NAND_DEVICE 1 |
| #define CFG_NAND_BASE (0xE7200000) |
| #define NAND_MAX_CHIPS 1 |
| |
| #define NAND_DISABLE_CE() (NFCONT_REG |= (1 << 1)) |
| #define NAND_ENABLE_CE() (NFCONT_REG &= ~(1 << 1)) |
| #define NF_TRANSRnB() do { while(!(NFSTAT_REG & (1 << 0))); } while(0) |
| |
| #define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
| #define CFG_NAND_WP 1 |
| #define CFG_NAND_YAFFS_WRITE 1 /* support yaffs write */ |
| |
| #define CFG_NAND_HWECC |
| #define CONFIG_NAND_BL1_8BIT_ECC |
| #undef CFG_NAND_FLASH_BBT |
| |
| /* IROM specific data */ |
| #define SDMMC_BLK_SIZE (0xd003a500) |
| #define COPY_SDMMC_TO_MEM (0xD003E008) |
| |
| /* SD/MMC configuration */ |
| //#define CONFIG_GENERIC_MMC |
| //#define CONFIG_S3C_HSMMC |
| #undef DEBUG_S3C_HSMMC |
| |
| /* The macro for MMC channel 0 is defined by default and can't be undefined */ |
| #define USE_MMC0 |
| #define USE_MMC2 |
| #define MMC_MAX_CHANNEL 4 |
| |
| /* |
| * SD/MMC detection takes a little long time |
| * So, you can ignore detection process for SD/MMC card |
| */ |
| #undef CONFIG_NO_SDMMC_DETECTION |
| |
| /* |
| * IDE/ATA stuff |
| */ |
| #if defined(CONFIG_CMD_IDE) |
| #undef CONFIG_IDE_LED /* no led for ide supported */ |
| #undef CONFIG_IDE_RESET /* no reset for ide supported */ |
| #define CONFIG_IDE_PREINIT |
| |
| #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drive per IDE bus */ |
| |
| #define CFG_ATA_BASE_ADDR 0xE8200000 |
| #define CFG_ATA_IDE0_OFFSET 0x0000 |
| #define CFG_ATA_DATA_OFFSET 0x0054 /* Offset for data I/O */ |
| #define CFG_ATA_REG_OFFSET 0x0054 /* Offset for normal register accesses */ |
| #define CFG_ATA_ALT_OFFSET 0x0054 /* Offset for alternate registers */ |
| #define CFG_ATA_STRIDE 4 /* CF.A0 --> CF.Ax */ |
| #endif /* CONFIG_CMD_IDE */ |
| |
| #define CONFIG_MTDPARTITION "80000 400000 3000000" |
| #define CONFIG_BOOTDELAY 3 |
| #define CONFIG_BOOTCOMMAND "movi read kernel c0008000;bootm c0008000" |
| /* OneNAND configuration */ |
| #define CFG_ONENAND_BASE (0xB0000000) |
| #define CFG_MAX_ONENAND_DEVICE 1 |
| |
| //#define CONFIG_BOOT_ONENAND_IROM |
| #define CONFIG_NAND |
| //#define CONFIG_BOOT_NAND |
| //#define CONFIG_ONENAND |
| #define ONENAND_REG_DBS_DFS_WIDTH (0x160) |
| #define ONENAND_REG_FLASH_AUX_CNTRL (0x300) |
| |
| #define GPNCON_OFFSET 0x830 |
| #define GPNDAT_OFFSET 0x834 |
| #define GPNPUD_OFFSET 0x838 |
| |
| #define CFG_ENV_IS_IN_AUTO |
| |
| #endif /* __CONFIG_H */ |
