| # SPDX-License-Identifier: GPL-2.0-only |
| |
| # ----------------------------------------------------------------- |
| entries |
| |
| # ----------------------------------------------------------------- |
| 0 120 r 0 reserved_memory |
| |
| # ----------------------------------------------------------------- |
| # RTC_BOOT_BYTE (coreboot hardcoded) |
| 384 1 e 4 boot_option |
| 388 4 h 0 reboot_counter |
| |
| # ----------------------------------------------------------------- |
| # coreboot config options: console |
| 395 4 e 6 debug_level |
| |
| # coreboot config options: cpu |
| |
| # coreboot config options: southbridge |
| 408 1 e 1 nmi |
| #409 2 e 7 power_on_after_fail |
| |
| # coreboot config options: northbridge |
| 411 3 e 11 gfx_uma_size |
| |
| # coreboot config options: bootloader |
| 416 512 s 0 boot_devices |
| 928 8 h 0 boot_default |
| 936 1 e 8 cmos_defaults_loaded |
| 937 1 e 1 lpt |
| |
| # coreboot config options: check sums |
| 984 16 h 0 check_sum |
| |
| # RAM initialization internal data |
| 1024 8 r 0 C0WL0REOST |
| 1032 8 r 0 C1WL0REOST |
| 1040 8 r 0 RCVENMT |
| 1048 4 r 0 C0DRT1 |
| 1052 4 r 0 C1DRT1 |
| |
| # ----------------------------------------------------------------- |
| |
| enumerations |
| |
| #ID value text |
| 1 0 Disable |
| 1 1 Enable |
| 2 0 Enable |
| 2 1 Disable |
| 4 0 Fallback |
| 4 1 Normal |
| 6 0 Emergency |
| 6 1 Alert |
| 6 2 Critical |
| 6 3 Error |
| 6 4 Warning |
| 6 5 Notice |
| 6 6 Info |
| 6 7 Debug |
| 6 8 Spew |
| 7 0 Disable |
| 7 1 Enable |
| 7 2 Keep |
| 8 0 No |
| 8 1 Yes |
| 9 0 Secondary |
| 9 1 Primary |
| 11 0 1M |
| 11 1 4M |
| 11 2 8M |
| 11 3 16M |
| 11 4 32M |
| 11 5 48M |
| 11 6 64M |
| |
| # ----------------------------------------------------------------- |
| checksums |
| |
| checksum 392 983 984 |
