UPSTREAM: mb/google/zork: update G2 TS RST delay time
in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even
rst delay time already meets spec definition: 10us (minimum).
Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine
on those specific m/b+BOE(G2 TS) panel.
BUG=b:159510906
BRANCH=trembyle-bringup
TEST=emerge-zork coreboot
boot with G2 TS, make sure G2 TS is functional
Change-Id: I7f91245ea0535364fffe7e8506d014aeb9a2c617
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 24e62217060b56e75cea67d17d251180eb0ad447
Original-Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590
Original-Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/42867
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2277640
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
(cherry picked from commit e07a5029202750f07fe341a0ea22b74e76118423)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2277951
Tested-by: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com>
diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index 18288ec..229469e 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -93,7 +93,7 @@
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
register "generic.probed" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
- register "generic.reset_delay_ms" = "1"
+ register "generic.reset_delay_ms" = "50"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end
