UPSTREAM: mb/google/brya/var/kinox: Modify DDR4 to non-interleaved
Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.
BUG=b:210094309
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Original-Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
GitOrigin-RevId: 5d3b1bbce4b3aefaee66e1d96be058397a9d7840
Change-Id: Id36fee99289944dfedb375ddbca15b914e65f4bb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3545616
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
Reviewed-by: Ricky Chang <rickytlchang@chromium.org>
Commit-Queue: Ricky Chang <rickytlchang@chromium.org>
diff --git a/src/mainboard/google/brya/variants/kinox/Makefile.inc b/src/mainboard/google/brya/variants/kinox/Makefile.inc
index 681c764..27174f4 100644
--- a/src/mainboard/google/brya/variants/kinox/Makefile.inc
+++ b/src/mainboard/google/brya/variants/kinox/Makefile.inc
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
+romstage-y += memory.c
ramstage-y += gpio.c
ramstage-y += ramstage.c
diff --git a/src/mainboard/google/brya/variants/kinox/memory.c b/src/mainboard/google/brya/variants/kinox/memory.c
new file mode 100644
index 0000000..ad33e9c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/kinox/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+ .type = MEM_TYPE_DDR4,
+
+ .rcomp = {
+ /* Baseboard uses only 100ohm Rcomp resistors */
+ .resistor = 100,
+
+ /* Baseboard Rcomp target values */
+ .targets = {50, 20, 25, 25, 25},
+ },
+
+ .ect = 1, /* Early Command Training */
+
+ .UserBd = BOARD_TYPE_MOBILE,
+
+ .ddr_config = {
+ .dq_pins_interleaved = false,
+ },
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+ return &ddr4_mem_config;
+}
