| chip soc/intel/skylake |
| |
| # Enable Panel as eDP and configure power delays |
| register "gpu_pp_up_delay_ms" = "210" # T3 |
| register "gpu_pp_down_delay_ms" = "500" # T10 |
| register "gpu_pp_cycle_delay_ms" = "5000" # T12 |
| register "gpu_pp_backlight_on_delay_ms" = "1" # T7 |
| register "gpu_pp_backlight_off_delay_ms" = "200" # T9 |
| |
| # Enable deep Sx states |
| register "deep_s3_enable_ac" = "1" |
| register "deep_s3_enable_dc" = "1" |
| register "deep_s5_enable_ac" = "1" |
| register "deep_s5_enable_dc" = "1" |
| register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| |
| register "eist_enable" = "1" |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| register "gpe0_dw0" = "GPP_C" |
| register "gpe0_dw1" = "GPP_D" |
| register "gpe0_dw2" = "GPP_E" |
| |
| register "gen1_dec" = "0x000c0081" |
| register "gen2_dec" = "0x000c0681" |
| register "gen3_dec" = "0x000c1641" |
| |
| # Disable DPTF |
| register "dptf_enable" = "0" |
| |
| # FSP Configuration |
| register "ProbelessTrace" = "0" |
| register "SataSalpSupport" = "1" |
| register "SataMode" = "0" |
| |
| # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 |
| register "SataPortsEnable[0]" = "1" |
| register "SataPortsEnable[1]" = "1" |
| register "SataPortsEnable[2]" = "1" |
| register "SataPortsDevSlp[0]" = "1" |
| register "SataPortsDevSlp[1]" = "1" |
| register "SataPortsDevSlp[2]" = "1" |
| register "DspEnable" = "0" |
| register "IoBufferOwnership" = "0" |
| register "SsicPortEnable" = "0" |
| register "ScsEmmcHs400Enabled" = "0" |
| register "PttSwitch" = "0" |
| register "SkipExtGfxScan" = "1" |
| register "HeciEnabled" = "1" |
| register "SaGv" = "SaGv_Enabled" |
| register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| register "PmConfigSlpS4MinAssert" = "1" # 1s |
| register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| register "PmConfigSlpAMinAssert" = "3" # 2s |
| register "PmTimerDisabled" = "0" |
| |
| register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| |
| register "PmConfigPciClockRun" = "1" |
| |
| # Enable Root Ports 3, 4 and 9 |
| register "PcieRpEnable[2]" = "1" # Ethernet controller |
| register "PcieRpClkReqSupport[2]" = "1" |
| register "PcieRpClkReqNumber[2]" = "0" |
| register "PcieRpClkSrcNumber[2]" = "0" |
| register "PcieRpAdvancedErrorReporting[2]" = "1" |
| register "PcieRpLtrEnable[2]" = "1" |
| |
| register "PcieRpEnable[3]" = "1" # Wireless controller |
| register "PcieRpClkReqSupport[3]" = "1" |
| register "PcieRpClkReqNumber[3]" = "1" |
| register "PcieRpClkSrcNumber[3]" = "1" |
| register "PcieRpAdvancedErrorReporting[3]" = "1" |
| register "PcieRpLtrEnable[3]" = "1" |
| |
| register "PcieRpEnable[8]" = "1" # NVMe controller |
| register "PcieRpClkReqSupport[8]" = "1" |
| register "PcieRpClkReqNumber[8]" = "4" |
| register "PcieRpClkSrcNumber[8]" = "4" |
| register "PcieRpAdvancedErrorReporting[8]" = "1" |
| register "PcieRpLtrEnable[8]" = "1" |
| |
| register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
| register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) |
| register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)" # FPR |
| register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # SD |
| register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # INT |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) |
| register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Webcam |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # mPCIe / WiFi Port |
| register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # mSATA / WWAN Port |
| |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) |
| |
| # PL1 override 25W |
| # PL2 override 44W |
| register "power_limits_config" = "{ |
| .tdp_pl1_override = 25, |
| .tdp_pl2_override = 44, |
| }" |
| |
| # Send an extra VR mailbox command for the PS4 exit issue |
| register "SendVrMbxCmd" = "2" |
| |
| # Lock Down |
| register "common_soc_config" = "{ |
| .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| }" |
| |
| device cpu_cluster 0 on |
| device lapic 0 on end |
| end |
| device domain 0 on |
| device pci 00.0 on end # Host Bridge |
| device pci 02.0 on end # Integrated Graphics Device |
| device pci 04.0 on end # SA thermal subsystem |
| device pci 14.0 on end # USB xHCI |
| device pci 14.1 off end # USB xDCI (OTG) |
| device pci 14.2 on end # Thermal Subsystem |
| device pci 14.3 off end # Camera |
| device pci 16.0 on end # Management Engine Interface 1 |
| device pci 16.1 off end # Management Engine Interface 2 |
| device pci 16.2 off end # Management Engine IDE-R |
| device pci 16.3 off end # Management Engine KT Redirection |
| device pci 16.4 off end # Management Engine Interface 3 |
| device pci 17.0 on end # SATA |
| device pci 1c.0 off end # PCI Express Port 1 |
| device pci 1c.1 off end # PCI Express Port 2 |
| device pci 1c.2 on end # PCI Express Port 3 |
| device pci 1c.3 on end # PCI Express Port 4 |
| device pci 1c.4 off end # PCI Express Port 5 |
| device pci 1c.5 off end # PCI Express Port 6 |
| device pci 1c.6 off end # PCI Express Port 7 |
| device pci 1c.7 off end # PCI Express Port 8 |
| device pci 1d.0 on end # PCI Express Port 9 |
| device pci 1d.1 off end # PCI Express Port 10 |
| device pci 1d.2 off end # PCI Express Port 11 |
| device pci 1d.3 off end # PCI Express Port 12 |
| device pci 1e.6 off end # SDXC |
| device pci 1f.0 on |
| chip ec/51nb/npce985la0dx |
| device pnp 0c09.0 on end |
| device pnp 4e.5 on end |
| device pnp 4e.6 on end |
| device pnp 4e.11 on end |
| end |
| end # LPC Interface |
| device pci 1f.1 off end # P2SB |
| device pci 1f.2 on end # Power Management Controller |
| device pci 1f.3 on end # Intel HDA |
| device pci 1f.4 on end # SMBus |
| device pci 1f.5 off end # PCH SPI |
| device pci 1f.6 off end # GbE |
| end |
| end |
