UPSTREAM: mb/sapphire/pureplatinumh61: Use custom SPI OPMENU
The SPI chip in this board needs a custom OPMENU, otherwise flashrom
fails halfway during the write.
From the default OPMENU, Block Erase (0xd8) has been replaced by AAI
write (0xad) and Fast Read (0x0b) by Write Disable (0x04).
BUG=none
BRANCH=none
TEST=none
Change-Id: I96382f24fd8cde26ae02b57fd5a91a5c2bd1c044
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e134db253589cff2f8c4cfba171a18c75430aad8
Original-Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/25551
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/1041908
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1 file changed
