tree 8d906a5294e4ad3501db2eaf4806a1024a5ca561
parent 1173c130e1f4c7b1e5c4d098af244b3c2788ecf7
author Nicola Corna <nicola@corna.info> 1522657626 +0200
committer chrome-bot <chrome-bot@chromium.org> 1525357401 -0700

UPSTREAM: mb/sapphire/pureplatinumh61: Use custom SPI OPMENU

The SPI chip in this board needs a custom OPMENU, otherwise flashrom
fails halfway during the write.

From the default OPMENU, Block Erase (0xd8) has been replaced by AAI
write (0xad) and Fast Read (0x0b) by Write Disable (0x04).

BUG=none
BRANCH=none
TEST=none

Change-Id: I96382f24fd8cde26ae02b57fd5a91a5c2bd1c044
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: e134db253589cff2f8c4cfba171a18c75430aad8
Original-Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320
Original-Signed-off-by: Nicola Corna <nicola@corna.info>
Original-Reviewed-on: https://review.coreboot.org/25551
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://chromium-review.googlesource.com/1041908
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>