UPSTREAM: soc/intel/cannonlake: Add 4E/4F to early io init
This is needed for the AST2500 to work, because it uses 4E/4F.
BUG=none
BRANCH=none
TEST=none
Change-Id: I432a50c2df13e4a6df4f2189ac7644c56d57f5c8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f4aa501ecacb3cbc3774d01b5f9209f71bd578cf
Original-Change-Id: Ie47474e9bf1edfe98555a148469c41283e9a4ea6
Original-Signed-off-by: Christian Walter <christian.walter@9elements.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/34862
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Original-Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1757016
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index c43d6d8..a3252c2 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -159,7 +159,7 @@
void pch_early_iorange_init(void)
{
- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
/* IO Decode Range */
