Documentation/Intel/Board/board.html - mirrors/cros/chromiumos/third_party/coreboot - Git at Google

 <!DOCTYPE html>
 <html>
   <head>
     <title>Board</title>
   </head>
   <body>

 <h1>x86 Board Development</h1>
 <p>
   Board development requires System-on-a-Chip (SoC) support.
   The combined steps are listed
   <a target="_blank" href="../development.html">here</a>.
   The development steps for the board are listed below:
 </p>
 <ol>
   <li><a href="#RequiredFiles">Required Files</a></li>
   <li>Enable <a href="#SerialOutput">Serial Output</a></li>
   <li>Load the <a href="#SpdData">Memory Timing Data</a></li>
   <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
   <li><a href="#AcpiTables">ACPI Tables</a></li>
 </ol>


 <hr>
 <h2><a name="RequiredFiles">Required Files</a></h2>
 <p>
   Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
 </p>

 <p>
   The following files are required to build a new board:
 </p>
 <ol>
   <li>Kconfig.name - Defines the Kconfig value for the board</li>
   <li>Kconfig
     <ol type="A">
       <li>Selects the SoC for the board and specifies the SPI flash size
         <ol type="I">
           <li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
           <li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
         </ol>
       </li>
       <li>Declare the Kconfig values for:
         <ol type="I">
           <li>MAINBOARD_DIR</li>
           <li>MAINBOARD_PART_NUMBER</li>
           <li>MAINBOARD_VENDOR</li>
         </ol>
       </li>
     </ol>
   </li>
   <li>devicetree.cb - Enable root bridge and serial port
     <ol type="A">
       <li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
         this path is used by the generated static.c to include the chip.h
         header file
       </li>
     </ol>
   </li>
   <li>romstage.c
     <ol type="A">
       <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
     </ol>
   </li>
   <li>Configure coreboot build:
     <ol type="A">
       <li>Set LOCALVERSION</li>
       <li>Select vendor for the board</li>
       <li>Select the board</li>
       <li>CBFS_SIZE = 0x00100000</li>
       <li>Set the CPU_MICROCODE_CBFS_LEN</li>
       <li>Set the CPU_MICROCODE_CBFS_LOC</li>
       <li>Set the FSP_IMAGE_ID_STRING</li>
       <li>Set the FSP_LOC</li>
       <li>No payload</li>
       <li>Choose the default value for all other options</li>
     </ol>
   </li>
 </ol>


 <hr>
 <h2><a name="SerialOutput">Enable Serial Output</a></h2>
 <p>
   Use the following steps to enable serial output:
 </p>
 <ol>
   <li>Implement the car_mainboard_pre_console_init routine in the com_init.c
     file:
     <ol type="A">
       <li>Power on and enable the UART controller</li>
       <li>Connect the UART receive and transmit data lines to the
         appropriate SoC pins
       </li>
     </ol>
   </li>
   <li>Add Makefile.inc
     <ol type="A">
       <li>Add com_init.c to romstage</li>
     </ol>
   </li>
 </ol>


 <hr>
 <h2><a name="SpdData">Memory Timing Data</a></h2>
 <p>
   Memory timing data is located in the flash.  This data is in the format of
   <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
   (SPD) data.
   Use the following steps to load the SPD data:
 </p>
 <ol>
   <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
     display of the SPD data being passed to MemoryInit
   </li>
   <li>Create an "spd" subdirectory</li>
   <li>Create an spd/spd.c file for the SPD implementation
     <ol type="A">
       <li>Implement the mainboard_fill_spd_data routine
         <ol type="i">
           <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
           <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
           <li>Set the DIMM channel configuration</li>
         </ol>
       </li>
     </ol>
   </li>
   <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
   <li>Create spd/Makefile.inc
     <ol type="A">
       <li>Add spd.c to romstage</li>
       <li>Add the .spd.hex file to SPD_SOURCES</li>
     </ol>
   </li>
   <li>Edit Makefile.inc to add the spd subdirectory</li>
   <li>Edit romstage.c
     <ol type="A">
       <li>Call mainboard_fill_spd_data</li>
       <li>Add mainboard_memory_init_params to copy the SPD and DRAM
         configuration data from the pei_data structure into the UPDs
         for MemoryInit
       </li>
     </ol>
   </li>
   <li>Edit devicetree.cb
     <ol type="A">
       <li>Include the UPD parameters for MemoryInit except for:
         <ul>
           <li>Address of SPD data</li>
           <li>DRAM configuration set above</li>
         </ul>
       </li>
     </ol>
   </li>
   <li>A working FSP
     <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
     routine is required to complete debugging</li>
   <li>Debug the result until port 0x80 outputs
     <ol type="A">
       <li>0x34:
         - Just after entering
         <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
       </li>
       <li>0x36:
         - Just before displaying the
         <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
         for FSP MemoryInit
       </li>
       <li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
         - Just before calling FSP
         <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
       </li>
       <li>0x37:
         - Just after returning from FSP
         <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
       </li>
     </ol>
   </li>
   <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
 </ol>


 <hr>
 <h2><a name="DisablePciDevices">Disable PCI Devices</a></h2>
 <p>
   Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
   of the devices in the system.  Edit the devicetree.cb file:
 </p>
 <ol>
   <li>Edit the devicetree.cb file:
     <ol type="A">
       <li>Add an entry for a PCI device.function and turn it off.  The entry
         should look similar to:
 <pre><code>device pci 14.0 off end</code></pre>
       </li>
       <li>Turn on the devices for:
         <ul>
           <li>Memory Controller</li>
           <li>Debug serial device</li>
         </ul>
       </li>
     </ol>
   </li>
   <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
 </ol>


 <hr>
 <h2><a name="AcpiTables">ACPI Tables</a></h2>
 <ol>
   <li>Edit Kconfig
     <ol type="A">
       <li>Add "select HAVE_ACPI_TABLES"</li>
     </ol>
   </li>
   <li>Add the acpi_tables.c module:
     <ol type="A">
       <li>Include soc/acpi.h</li>
       <li>Add the acpi_create_fadt routine
         <ol type="I">
           <li>fill in the ACPI header</li>
           <li>Call the acpi_fill_in_fadt routine</li>
         </ol>
       </li>
     </ol>
   </li>
   <li>Add the dsdt.asl module:
   </li>
 </ol>


 <hr>
 <p>Modified: 20 February 2016</p>
   </body>
 </html>
	<!DOCTYPE html>
	<html>
	<head>
	<title>Board</title>
	</head>
	<body>

	<h1>x86 Board Development</h1>
	<p>
	Board development requires System-on-a-Chip (SoC) support.
	The combined steps are listed
	<a target="_blank" href="../development.html">here</a>.
	The development steps for the board are listed below:
	</p>
	<ol>
	<li><a href="#RequiredFiles">Required Files</a></li>
	<li>Enable <a href="#SerialOutput">Serial Output</a></li>
	<li>Load the <a href="#SpdData">Memory Timing Data</a></li>
	<li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
	<li><a href="#AcpiTables">ACPI Tables</a></li>
	</ol>


	<hr>
	<h2><a name="RequiredFiles">Required Files</a></h2>
	<p>
	Create the board directory as src/mainboard/<Vendor>/<Board>.
	</p>

	<p>
	The following files are required to build a new board:
	</p>
	<ol>
	<li>Kconfig.name - Defines the Kconfig value for the board</li>
	<li>Kconfig
	<ol type="A">
	<li>Selects the SoC for the board and specifies the SPI flash size
	<ol type="I">
	<li>BOARD_ROMSIZE_KB_<Size></li>
	<li>SOC_<Vendor>_<Chip Family></li>
	</ol>
	</li>
	<li>Declare the Kconfig values for:
	<ol type="I">
	<li>MAINBOARD_DIR</li>
	<li>MAINBOARD_PART_NUMBER</li>
	<li>MAINBOARD_VENDOR</li>
	</ol>
	</li>
	</ol>
	</li>
	<li>devicetree.cb - Enable root bridge and serial port
	<ol type="A">
	<li>The first line must be "chip soc/Intel/<soc family>";
	this path is used by the generated static.c to include the chip.h
	header file
	</li>
	</ol>
	</li>
	<li>romstage.c
	<ol type="A">
	<li>Add routine mainboard_romstage_entry which calls romstage_common</li>
	</ol>
	</li>
	<li>Configure coreboot build:
	<ol type="A">
	<li>Set LOCALVERSION</li>
	<li>Select vendor for the board</li>
	<li>Select the board</li>
	<li>CBFS_SIZE = 0x00100000</li>
	<li>Set the CPU_MICROCODE_CBFS_LEN</li>
	<li>Set the CPU_MICROCODE_CBFS_LOC</li>
	<li>Set the FSP_IMAGE_ID_STRING</li>
	<li>Set the FSP_LOC</li>
	<li>No payload</li>
	<li>Choose the default value for all other options</li>
	</ol>
	</li>
	</ol>


	<hr>
	<h2><a name="SerialOutput">Enable Serial Output</a></h2>
	<p>
	Use the following steps to enable serial output:
	</p>
	<ol>
	<li>Implement the car_mainboard_pre_console_init routine in the com_init.c
	file:
	<ol type="A">
	<li>Power on and enable the UART controller</li>
	<li>Connect the UART receive and transmit data lines to the
	appropriate SoC pins
	</li>
	</ol>
	</li>
	<li>Add Makefile.inc
	<ol type="A">
	<li>Add com_init.c to romstage</li>
	</ol>
	</li>
	</ol>


	<hr>
	<h2><a name="SpdData">Memory Timing Data</a></h2>
	<p>
	Memory timing data is located in the flash. This data is in the format of
	<a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
	(SPD) data.
	Use the following steps to load the SPD data:
	</p>
	<ol>
	<li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
	display of the SPD data being passed to MemoryInit
	</li>
	<li>Create an "spd" subdirectory</li>
	<li>Create an spd/spd.c file for the SPD implementation
	<ol type="A">
	<li>Implement the mainboard_fill_spd_data routine
	<ol type="i">
	<li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
	<li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
	<li>Set the DIMM channel configuration</li>
	</ol>
	</li>
	</ol>
	</li>
	<li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
	<li>Create spd/Makefile.inc
	<ol type="A">
	<li>Add spd.c to romstage</li>
	<li>Add the .spd.hex file to SPD_SOURCES</li>
	</ol>
	</li>
	<li>Edit Makefile.inc to add the spd subdirectory</li>
	<li>Edit romstage.c
	<ol type="A">
	<li>Call mainboard_fill_spd_data</li>
	<li>Add mainboard_memory_init_params to copy the SPD and DRAM
	configuration data from the pei_data structure into the UPDs
	for MemoryInit
	</li>
	</ol>
	</li>
	<li>Edit devicetree.cb
	<ol type="A">
	<li>Include the UPD parameters for MemoryInit except for:
	<ul>
	<li>Address of SPD data</li>
	<li>DRAM configuration set above</li>
	</ul>
	</li>
	</ol>
	</li>
	<li>A working FSP
	<a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
	routine is required to complete debugging</li>
	<li>Debug the result until port 0x80 outputs
	<ol type="A">
	<li>0x34:
	- Just after entering
	<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
	</li>
	<li>0x36:
	- Just before displaying the
	<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
	for FSP MemoryInit
	</li>
	<li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
	- Just before calling FSP
	<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
	</li>
	<li>0x37:
	- Just after returning from FSP
	<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
	</li>
	</ol>
	</li>
	<li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
	</ol>



	<hr>
	<h2><a name="DisablePciDevices">Disable PCI Devices</a></h2>
	<p>
	Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
	of the devices in the system. Edit the devicetree.cb file:
	</p>
	<ol>
	<li>Edit the devicetree.cb file:
	<ol type="A">
	<li>Add an entry for a PCI device.function and turn it off. The entry
	should look similar to:
	<pre><code>device pci 14.0 off end</code></pre>
	</li>
	<li>Turn on the devices for:
	<ul>
	<li>Memory Controller</li>
	<li>Debug serial device</li>
	</ul>
	</li>
	</ol>
	</li>
	<li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
	</ol>



	<hr>
	<h2><a name="AcpiTables">ACPI Tables</a></h2>
	<ol>
	<li>Edit Kconfig
	<ol type="A">
	<li>Add "select HAVE_ACPI_TABLES"</li>
	</ol>
	</li>
	<li>Add the acpi_tables.c module:
	<ol type="A">
	<li>Include soc/acpi.h</li>
	<li>Add the acpi_create_fadt routine
	<ol type="I">
	<li>fill in the ACPI header</li>
	<li>Call the acpi_fill_in_fadt routine</li>
	</ol>
	</li>
	</ol>
	</li>
	<li>Add the dsdt.asl module:
	</li>
	</ol>



	<hr>
	<p>Modified: 20 February 2016</p>
	</body>
	</html>