UPSTREAM: AGESA f15 vendorcode: Remove unused sources
BUG=none
BRANCH=none
TEST=none
Change-Id: I1d57333e7309406a28d129ef55569c6ea077be1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5bf3457bc470b4cc67d1c3ad55c8543305e320f0
Original-Change-Id: Id1ed36e7e76d25cdc9e86254b108deaca0f8b423
Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/21265
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <f4bug@amsat.org>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/645073
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
deleted file mode 100644
index 414c716..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
+++ /dev/null
@@ -1,1037 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 01000085 for 1040 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 01000085 for 1040 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085 =
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-}};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
deleted file mode 100644
index 8bda08c..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
+++ /dev/null
@@ -1,1037 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c6 for 1041 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c6 for 1041 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6 =
-{{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc6,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xb5,
-0x66,
-0x0e,
-0x84,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x41,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0xa0,
-0x09,
-0x00,
-0x00,
-0xa5,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xa1,
-0x09,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x97,
-0xd1,
-0x7f,
-0x00,
-0x83,
-0x3f,
-0x36,
-0xc0,
-0xa0,
-0x1b,
-0xf8,
-0x13,
-0x0e,
-0xbf,
-0x0c,
-0xb4,
-0xf2,
-0x1f,
-0xf8,
-0xa7,
-0x3c,
-0xfc,
-0x03,
-0xfc,
-0x40,
-0x03,
-0x54,
-0x00,
-0x92,
-0xff,
-0xe0,
-0xbf,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x5f,
-0x9e,
-0xfa,
-0xff,
-0x9f,
-0x87,
-0x7f,
-0x80,
-0x03,
-0xf8,
-0xff,
-0xc6,
-0x01,
-0x0e,
-0xfc,
-0xbd,
-0x00,
-0xa0,
-0x2a,
-0x69,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x00,
-0x5a,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0x1c,
-0x9c,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0xf0,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0x5c,
-0x56,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x00,
-0x61,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xfb,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfd,
-0x6b,
-0x00,
-0xa0,
-0xff,
-0xfe,
-0xff,
-0xcb,
-0xf0,
-0xef,
-0xf5,
-0x7f,
-0x8f,
-0x40,
-0x3f,
-0x00,
-0x83,
-0xbf,
-0xb7,
-0xd7,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0xe4,
-0x7f,
-0xf9,
-0x0f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x00,
-0xf0,
-0x32,
-0x19,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0x7f,
-0xe0,
-0x1f,
-0xc0,
-0xf0,
-0x0f,
-0xe0,
-0xdf,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
deleted file mode 100644
index 3f1ec05..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
+++ /dev/null
@@ -1,1037 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c7 for 1062 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c7 for 1062 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7 =
-{{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc7,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0xb8,
-0x53,
-0x63,
-0x1d,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x62,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x9a,
-0x0b,
-0x00,
-0x00,
-0x16,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x6f,
-0x58,
-0x39,
-0x00,
-0x81,
-0x3f,
-0xa0,
-0xd7,
-0x04,
-0x00,
-0xfc,
-0xb7,
-0x0f,
-0xff,
-0x58,
-0xf7,
-0x72,
-0xc0,
-0xff,
-0x6f,
-0x3c,
-0xfc,
-0x03,
-0xfc,
-0xc0,
-0x18,
-0xd5,
-0x00,
-0x80,
-0xff,
-0x66,
-0x3c,
-0xeb,
-0xc0,
-0x9f,
-0xd9,
-0x4d,
-0xee,
-0xf8,
-0xff,
-0xff,
-0x83,
-0x7f,
-0xa6,
-0x07,
-0xe8,
-0xff,
-0xff,
-0xe8,
-0x1f,
-0xbe,
-0xb5,
-0x00,
-0x60,
-0x2f,
-0x6a,
-0xbf,
-0xe8,
-0x04,
-0xff,
-0xf5,
-0xf3,
-0xf0,
-0xaf,
-0x7a,
-0x00,
-0xff,
-0xd9,
-0x31,
-0xc0,
-0x83,
-0x3f,
-0xff,
-0x03,
-0x88,
-0xff,
-0x58,
-0xc8,
-0x0f,
-0xef,
-0x35,
-0x00,
-0xd0,
-0x00,
-0xfb,
-0xbf,
-0x85,
-0xff,
-0x03,
-0xd8,
-0x72,
-0xf8,
-0xad,
-0x1c,
-0x80,
-0xfb,
-0x1f,
-0xc0,
-0xe7,
-0xa0,
-0xbe,
-0x71,
-0x00,
-0x86,
-0x7f,
-0x40,
-0xaf,
-0x07,
-0xff,
-0x1e,
-0x00,
-0xf8,
-0x6f,
-0x95,
-0x03,
-0x50,
-0xf4,
-0x03,
-0xf8,
-0x1c,
-0xf8,
-0xff,
-0x3f,
-0x00,
-0xf0,
-0xee,
-0x84,
-0xfc,
-0xfe,
-0xff,
-0xff,
-0x22,
-0xc3,
-0x1f,
-0x51,
-0x96,
-0x50,
-0x16,
-0x0d,
-0x00,
-0xf8,
-0xfe,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe5,
-0xa6,
-0xff,
-0x1f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfa,
-0xbf,
-0x07,
-0x01,
-0xfc,
-0x3f,
-0xe3,
-0x3e,
-0x0f,
-0xfd,
-0x50,
-0x03,
-0xb0,
-0xdf,
-0x8c,
-0xf9,
-0x3c,
-0xf4,
-0x43,
-0x0e,
-0xc0,
-0xfd,
-0x32,
-0xe5,
-0xf3,
-0xd0,
-0x0f,
-0x03,
-0x00,
-0xfb,
-0x24,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0xf0,
-0x0f,
-0xe0,
-0x3f,
-0x07,
-0xf0,
-0x6f,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0xff,
-0xff,
-0x00,
-0xfd,
-0xbb,
-0x14,
-0xf2,
-0xc3,
-0x2f,
-0xf8,
-0x13,
-0xcc,
-0x7f,
-0x0c,
-0xb8,
-0x0e,
-0x74,
-0xf5,
-0x03,
-0xf0,
-0xf8,
-0x33,
-0x03,
-0x1c,
-0x2b,
-0xd7,
-0x00,
-0x00,
-0xeb,
-0xe5,
-0x1f,
-0x80,
-0xc0,
-0x1f,
-0x1b,
-0xe0,
-0x9e,
-0x9b,
-0x7f,
-0x00,
-0x03,
-0x7f,
-0x6c,
-0x80,
-0xf8,
-0x7d,
-0xfe,
-0x01,
-0x0e,
-0xfc,
-0xb1,
-0x01,
-0xe0,
-0x6d,
-0x62,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x00,
-0xfa,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfc,
-0x6b,
-0x00,
-0xe0,
-0xfc,
-0xff,
-0x3f,
-0xcb,
-0xf0,
-0x8f,
-0x75,
-0xff,
-0xe5,
-0xff,
-0xff,
-0x2c,
-0xc3,
-0x3f,
-0xd6,
-0xf5,
-0x1c,
-0xf0,
-0xff,
-0x8b,
-0x0f,
-0xff,
-0x00,
-0x3f,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0xe0,
-0xbf,
-0x18,
-0x0f,
-0x3a,
-0xf0,
-0x27,
-0xf6,
-0xd1,
-0x35,
-0xfe,
-0x7f,
-0xe7,
-0xe1,
-0x9f,
-0xe8,
-0x5f,
-0xc6,
-0xff,
-0xff,
-0xeb,
-0x87,
-0x7f,
-0xaf,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x07,
-0xf0,
-0xbf,
-0xad,
-0x03,
-0x3c,
-0xf8,
-0x13,
-0x1f,
-0xc0,
-0x7f,
-0xf6,
-0x45,
-0xff,
-0xf0,
-0xad,
-0xff,
-0x04,
-0xff,
-0xff,
-0x83,
-0xad,
-0xc3,
-0x2f,
-0x04,
-0x00,
-0x2c,
-0x80,
-0xfe,
-0x03,
-0xf8,
-0xff,
-0xb5,
-0xe8,
-0x1f,
-0xbe,
-0xff,
-0xdf,
-0x65,
-0xfc,
-0x07,
-0x38,
-0x6b,
-0xf8,
-0xee,
-0xbf,
-0x96,
-0xff,
-0x5f,
-0xeb,
-0xff,
-0xe1,
-0xbf,
-0x07,
-0x00,
-0xfe,
-0x07,
-0xfe,
-0xb5,
-0xfc,
-0xbf,
-0x5a,
-0x57,
-0x0e,
-0xbf,
-0xad,
-0x07,
-0xf0,
-0xf4,
-0x13,
-0xf9,
-0x3c,
-0xf8,
-0x80,
-0x3f,
-0x81,
-0xf0,
-0xcb,
-0x60,
-0xeb,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0xb7,
-0xf5,
-0x00,
-0x07,
-0x7f,
-0x62,
-0x80,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1f,
-0xbe,
-0xb5,
-0xe8,
-0x60,
-0x7c,
-0xc0,
-0x9f,
-0x75,
-0xf8,
-0x65,
-0xb0,
-0x00,
-0x04,
-0x90,
-0x00,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
deleted file mode 100644
index 46ab18d..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
+++ /dev/null
@@ -1,1037 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000c8 for 1043 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000c8 for 1043 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8 =
-{{
-0x10,
-0x20,
-0x11,
-0x03,
-0xc8,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0x6a,
-0x99,
-0x77,
-0xef,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x43,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x10,
-0x0c,
-0x00,
-0x00,
-0x55,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0x51,
-0x03,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0x18,
-0x80,
-0x38,
-0xc0,
-0x83,
-0x37,
-0x80,
-0xff,
-0xb8,
-0xff,
-0xff,
-0x13,
-0x0e,
-0xbf,
-0x0c,
-0xb6,
-0x7a,
-0xc4,
-0xff,
-0x2f,
-0x3c,
-0xfc,
-0x6b,
-0xfd,
-0x40,
-0x03,
-0xd4,
-0x00,
-0x97,
-0xff,
-0xff,
-0xff,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x00,
-0xfe,
-0xbf,
-0xf5,
-0x9f,
-0x87,
-0x7e,
-0x22,
-0x01,
-0xc6,
-0x00,
-0xc4,
-0x7c,
-0x1e,
-0xfa,
-0x01,
-0x00,
-0xe0,
-0xff,
-0x7b,
-0x0e,
-0x40,
-0xbd,
-0x55,
-0xe0,
-0x73,
-0xd0,
-0x0f,
-0xff,
-0x00,
-0xe0,
-0xff,
-0x13,
-0xf2,
-0xc3,
-0xbb,
-0xff,
-0x8b,
-0xf8,
-0xff,
-0x44,
-0x59,
-0x0e,
-0x7f,
-0x34,
-0x00,
-0x70,
-0x59,
-0xfb,
-0x07,
-0xe0,
-0xfb,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0xfe,
-0x7f,
-0x94,
-0x9b,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0xff,
-0x1e,
-0x00,
-0xe8,
-0xff,
-0x8c,
-0x07,
-0xf0,
-0xf4,
-0x43,
-0xf9,
-0x3c,
-0x7e,
-0x33,
-0x0e,
-0xc0,
-0xd0,
-0x0f,
-0xe5,
-0xf3,
-0xf7,
-0xcb,
-0x38,
-0x00,
-0x43,
-0x3f,
-0x94,
-0xcf,
-0xec,
-0x93,
-0x0c,
-0x00,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0x3f,
-0xf0,
-0x0f,
-0x6f,
-0xf8,
-0x07,
-0xf0,
-0x80,
-0xff,
-0xc0,
-0x3f,
-0xbf,
-0xe1,
-0x1f,
-0xc0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0x03,
-0xf4,
-0xff,
-0xff,
-0xc8,
-0x0f,
-0xef,
-0x52,
-0x4f,
-0x70,
-0xbf,
-0xe0,
-0xe0,
-0x3a,
-0xfc,
-0x31,
-0x0f,
-0xc0,
-0xd3,
-0xd5,
-0x0c,
-0x70,
-0xe0,
-0xcf,
-0x03,
-0x00,
-0xac,
-0x5c,
-0x7f,
-0x00,
-0xae,
-0x97,
-0x6c,
-0x80,
-0x03,
-0x7f,
-0xfe,
-0x01,
-0x78,
-0x6e,
-0xb1,
-0x01,
-0x0e,
-0xfc,
-0xf9,
-0x07,
-0xe0,
-0xf7,
-0xc7,
-0x06,
-0x38,
-0xf0,
-0x8b,
-0x01,
-0x00,
-0x5e,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0x1f,
-0xf8,
-0x07,
-0xf0,
-0xfc,
-0x03,
-0xf8,
-0x37,
-0xff,
-0xf7,
-0x00,
-0xc0,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0x0f,
-0xfc,
-0x03,
-0x1b,
-0xfe,
-0x01,
-0xfc,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xd7,
-0x00,
-0x80,
-0xf8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0xfc,
-0x6b,
-0x00,
-0x20,
-0x04,
-0xff,
-0xbf,
-0xe8,
-0xf0,
-0xaf,
-0xf5,
-0xf3,
-0xff,
-0xd9,
-0x7a,
-0x00,
-0x83,
-0x3f,
-0x31,
-0xc0,
-0x0c,
-0x7d,
-0xe3,
-0x00,
-0x0f,
-0xfe,
-0x80,
-0x5e,
-0xf0,
-0xff,
-0x3d,
-0x00,
-0x65,
-0xfe,
-0xff,
-0x9f,
-0x7f,
-0xf8,
-0xc7,
-0xba,
-0x96,
-0xf2,
-0xff,
-0x7f,
-0xfa,
-0xe1,
-0x1f,
-0xeb,
-0x45,
-0x0e,
-0xf8,
-0xff,
-0x9f,
-0x87,
-0x7f,
-0x80,
-0x00,
-0xf8,
-0xff,
-0x1e,
-0x07,
-0xf0,
-0x5f,
-0x8c,
-0x7b,
-0x1d,
-0xf8,
-0x13,
-0xbf,
-0xe8,
-0x1a,
-0xff,
-0xf4,
-0xf3,
-0xf0,
-0x4f,
-0xff,
-0x2f,
-0xe3,
-0xff,
-0xd7,
-0xf5,
-0xc3,
-0xbf,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xd6,
-0x03,
-0xf8,
-0xdf,
-0x89,
-0x01,
-0x1e,
-0xfc,
-0xfb,
-0x0f,
-0xe0,
-0x3f,
-0xd6,
-0xa2,
-0x7f,
-0xf8,
-0xff,
-0x7f,
-0x82,
-0xff,
-0x97,
-0xc1,
-0xd6,
-0xe1,
-0x40,
-0x02,
-0x00,
-0x14,
-0x7f,
-0xff,
-0x01,
-0xfc,
-0xdf,
-0x5a,
-0xf4,
-0x0f,
-0xfe,
-0xff,
-0xef,
-0x32,
-0xfc,
-0x03,
-0x9c,
-0x35,
-0x7f,
-0xf7,
-0x5f,
-0xcb,
-0xf0,
-0xaf,
-0xf5,
-0xff,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0x5a,
-0x87,
-0x5f,
-0xad,
-0x2b,
-0xf8,
-0xdf,
-0xd6,
-0x03,
-0x1e,
-0xfa,
-0x89,
-0x7c,
-0x20,
-0x7d,
-0xc0,
-0x9f,
-0x75,
-0xf8,
-0x65,
-0xb0,
-0x80,
-0xff,
-0xef,
-0x01,
-0x00,
-0xff,
-0xdb,
-0x7a,
-0xc0,
-0x83,
-0x3f,
-0x31,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xf4,
-0x0f,
-0xdf,
-0x5a,
-0x4f,
-0xa0,
-0x3e,
-0xe0,
-0xd8,
-0x3a,
-0xfc,
-0x32,
-0x00,
-0xc0,
-0x01,
-0x48,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
deleted file mode 100644
index 7b413ac..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
+++ /dev/null
@@ -1,439 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
-{
-// 0x60:0x68
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x60, 0x68, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }}
- },
-// 0x70:0x78
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x70, 0x78, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }}
- },
-// Erratum 354
-// 0x40:48
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_C2 | AMD_F10_C3) // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL0_HT3, //
- 0x40, 0x48, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }}
- },
-// 0x50:0x58
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- (AMD_F10_C2 | AMD_F10_C3) // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL1_HT3, //
- 0x50, 0x58, // Address
- 0x00000040, // regData
- 0x00000040, // regMask
- }}
- },
-// 0xC0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL0_ALL, //
- 0xC0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }}
- },
-// 0xD0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL1_ALL, //
- 0xD0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }}
- },
-// 0xCF
-// FIFO_PTR_OPT_VALUE
- {
- HtPhyProfileRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- PERFORMANCE_NB_PSTATES_ENABLE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xCF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }}
- },
-// 0xDF
-// FIFO_PTR_OPT_VALUE
- {
- HtPhyProfileRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- PERFORMANCE_NB_PSTATES_ENABLE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xDF, // Address
- 0x0000004A, // regData
- 0x000000FF, // regMask
- }}
- },
-// 0x520A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x520A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }}
- },
-// 0x530A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x530A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }}
- },
-
-
-
-
-//
-// Deemphasis Settings
-//
-
-// For C3, also set [7]TxLs23ClkGateEn.
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }}
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevCHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
deleted file mode 100644
index 3f99c9d..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 HW C1e feature support functions.
- *
- * Provides the functions necessary to initialize the hardware C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuHwC1e.h"
-#include "cpuApicUtilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "cpuFamilyTranslation.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeHwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should hardware C1e be enabled
- *
- * @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE HW C1e is supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsHwC1eSupported (
- IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 PackageType;
- CPU_LOGICAL_ID LogicalId;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-
- if (((LogicalId.Revision & AMD_F10_RB_ALL) & ~(AMD_F10_RB_C3)) != 0) {
- return FALSE;
- }
-
- // Check if it is BL C2 (not S1g3)
- if ((LogicalId.Revision & AMD_F10_BL_C2) != 0) {
- PackageType = LibAmdGetPackageType (StdHeader);
- if (PackageType != PACKAGE_TYPE_S1G3) {
- return FALSE;
- }
- }
- return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Hardware C1e on a family 10h CPU.
- *
- * @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeHwC1e (
- IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 C1eData;
- UINT64 LocalMsrRegister;
- AP_TASK TaskPtr;
-
- LocalMsrRegister = 0;
- C1eData = PlatformConfig->C1ePlatformData;
-
- if (PlatformConfig->C1eMode == C1eModeAuto) {
- C1eData = PlatformConfig->C1ePlatformData3;
- }
-
- ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = C1eData;
- ((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 1;
- ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 1;
- ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0;
-
- TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Hardware C1e on a family 10h core.
- *
- * @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeHwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 LocalMsrRegister;
-
- // Enable C1e
- LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
-
- // Set OS Visible Workaround Status BIT1 to indicate that C1e
- // is enabled.
- LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
- LocalMsrRegister |= BIT1;
- LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
-}
-
-
-CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
-{
- 0,
- F10IsHwC1eSupported,
- F10InitializeHwC1e
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
deleted file mode 100644
index f77841c..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MSR_LS_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- (1 << 1), // NAND Mask
- }}
- },
-
-// MSR_BU_CFG (0xC0011023)
-// bit[21] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_B0 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MSR_BU_CFG, // MSR Address
- (1 << 21), // OR Mask
- (1 << 21), // NAND Mask
- }}
- },
-
-// MSR_BU_CFG2 (0xC001102A)
-// bit[50] = 1
-// For GH rev C1 and later [RdMmExtCfgQwEn]=1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_C0 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MSR_BU_CFG2, // MSR Address
- 0x0004000000000000, // OR Mask
- 0x0004000000000000, // NAND Mask
- }}
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
- AllCores,
- (sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
deleted file mode 100644
index 266dd21..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev C PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/RevC
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "F10PackageType.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
-{
-// Function 2 - DRAM Controller
-
-// F2x1B0 - Extended Memory Controller Configuration Low Register
-//
-// bit[5:4], AdapPrefNegativeStep = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
- 0x00000000, // regData
- 0x00000030, // regMask
- }}
- },
-// Function 3 - Misc. Control
-
-// F3x158 - Link to XCS Token Count
-// bits[3:0] LnkToXcsDRToken = 3
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_GT_A2 // CpuRevision
- },
- {AMD_PF_UMA}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
- 0x00000003, // regData
- 0x0000000F, // regMask
- }}
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C2
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 1
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000E681, // regData
- 0x0000FFFF, // regMask
- }}
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 4
- {
- HtFeatPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_SINGLE_LINK}, // platformFeatures
- {{
- HT_HOST_FEAT_HT1, // link feats
- PACKAGE_TYPE_ASB2, // package type
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x00008700, // regData
- 0x0000FF00, // regMask
- }}
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 1
-// bits[7:5] ClkDivisor = 7
- {
- ProfileFixup,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_C3 // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000F600, // regData
- 0x0000FF00, // regMask
- }}
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 4
- {
- HtFeatPciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_SINGLE_LINK}, // platformFeatures
- {{
- HT_HOST_FEAT_HT1, // link feats
- PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2), // package type
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x00008700, // regData
- 0x0000FF00, // regMask
- }}
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 5
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00005000, // regData
- 0x00007000, // regMask
- }}
- },
-// F3x180 - NB Extended Configuration
-// bits[23] SyncFloodOnDramTempErr = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
- 0x00800000, // regData
- 0x00800000, // regMask
- }}
- },
-// F3x188 - NB Extended Configuration Low Register
-// bit[22] = DisHldReg2
-// Errata #346
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Cx // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x00400000, // regData
- 0x00400000, // regMask
- }}
- }
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevCPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
deleted file mode 100644
index 104d3a1..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 SW C1e feature support functions.
- *
- * Provides the functions necessary to initialize the software C1e feature.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "cpuRegisters.h"
-#include "cpuSwC1e.h"
-#include "cpuApicUtilities.h"
-#include "cpuF10PowerMgmt.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-VOID
-STATIC
-F10InitializeSwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Should software C1e be enabled
- *
- * @param[in] SwC1eServices Pointer to this CPU's SW C1e family services.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @retval TRUE SW C1e is supported.
- *
- */
-BOOLEAN
-STATIC
-F10IsSwC1eSupported (
- IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- return TRUE;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Software C1e on a family 10h CPU.
- *
- * @param[in] SwC1eServices Pointer to this CPU's SW C1e family services.
- * @param[in] EntryPoint Timepoint designator.
- * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
- * @param[in] StdHeader Config Handle for library, services.
- *
- * @return AGESA_SUCCESS Always succeeds.
- *
- */
-AGESA_STATUS
-STATIC
-F10InitializeSwC1e (
- IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
- IN UINT64 EntryPoint,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 LocalMsrRegister;
- AP_TASK TaskPtr;
-
- LocalMsrRegister = 0;
- ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
- ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
- ((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 0;
- ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0;
- ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 1;
-
- TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
- TaskPtr.DataTransfer.DataSizeInDwords = 2;
- TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
- TaskPtr.DataTransfer.DataTransferFlags = 0;
- TaskPtr.ExeFlags = WAIT_FOR_CORE;
- ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Enable Software C1e on a family 10h core.
- *
- * @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0.
- * @param[in] StdHeader Config Handle for library, services.
- *
- */
-VOID
-STATIC
-F10InitializeSwC1eOnCore (
- IN VOID *IntPendMsr,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT64 LocalMsrRegister;
-
- // Enable C1e
- LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
-
- // Set OS Visible Workaround Status BIT1 to indicate that C1e
- // is enabled.
- LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
- LocalMsrRegister |= BIT1;
- LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
-}
-
-
-CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e =
-{
- 0,
- F10IsSwC1eSupported,
- F10InitializeSwC1e
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
deleted file mode 100644
index dd87ad3..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 revision Cx specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h rev C.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "GeneralServices.h"
-#include "cpuEarlyInit.h"
-#include "cpuPostInit.h"
-#include "cpuFeatures.h"
-#include "OptionMultiSocket.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set down core register on a revision C processor.
- *
- * This function set F3x190 Downcore Control Register[5:0]
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket Socket ID.
- * @param[in] Module Module ID in socket.
- * @param[in] LeveledCores Number of core.
- * @param[in] CoreLevelMode Core level mode.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Down Core register is updated.
- * @retval FALSE Down Core register is not updated.
- */
-BOOLEAN
-F10CommonRevCSetDownCoreRegister (
- IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT32 *Socket,
- IN UINT32 *Module,
- IN UINT32 *LeveledCores,
- IN CORE_LEVELING_TYPE CoreLevelMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempVar32_a;
- UINT32 CoreDisableBits;
- PCI_ADDR PciAddress;
- BOOLEAN IsUpdated;
- AGESA_STATUS AgesaStatus;
-
- IsUpdated = FALSE;
-
- switch (*LeveledCores) {
- case 1:
- CoreDisableBits = DOWNCORE_MASK_SINGLE;
- break;
- case 2:
- CoreDisableBits = DOWNCORE_MASK_DUAL;
- break;
- case 3:
- CoreDisableBits = DOWNCORE_MASK_TRI;
- break;
- default:
- CoreDisableBits = 0;
- break;
- }
-
- if (CoreDisableBits != 0) {
- if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
-
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- TempVar32_a = (TempVar32_a >> 12) & 0x3;
- if (TempVar32_a == 0) {
- CoreDisableBits &= 0x1;
- } else if (TempVar32_a == 1) {
- CoreDisableBits &= 0x3;
- } else if (TempVar32_a == 2) {
- CoreDisableBits &= 0x7;
- } else if (TempVar32_a == 3) {
- CoreDisableBits &= 0x0F;
- }
- PciAddress.Address.Register = DOWNCORE_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
- TempVar32_a |= CoreDisableBits;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- IsUpdated = TRUE;
- }
- }
- }
-
- return IsUpdated;
-}
-
-
-CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
-{
- 0,
- F10CommonRevCSetDownCoreRegister
-};
-
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU pstate current on a revision C processor.
- *
- * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
- *
- * This function returns the ProcIddMax.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Pstate The P-state to check.
- * @param[out] ProcIddMax P-state current in mA.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE P-state is enabled
- * @retval FALSE P-state is disabled
- */
-BOOLEAN
-F10CommonRevCGetProcIddMax (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 Pstate,
- OUT UINT32 *ProcIddMax,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 IddDiv;
- UINT32 CmpCap;
- UINT32 LocalPciRegister;
- UINT32 MsrAddress;
- UINT32 SinglePlaneNbIdd;
- UINT64 PstateMsr;
- BOOLEAN IsPstateEnabled;
- PCI_ADDR PciAddress;
-
- IsPstateEnabled = FALSE;
-
- MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
-
- ASSERT (MsrAddress <= PS_MAX_REG);
-
- LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
- if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
- OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
- CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
- CmpCap++;
-
- switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
- case 0:
- IddDiv = 1000;
- break;
- case 1:
- IddDiv = 100;
- break;
- case 2:
- IddDiv = 10;
- break;
- default: // IddDiv = 3 is reserved. Use 10
- ASSERT (FALSE);
- IddDiv = 10;
- break;
- }
-
- PciAddress.Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
- if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 1) {
- *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
- } else {
- PciAddress.Address.Register = PRCT_INFO_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
- SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->SinglePlaneNbIdd;
- SinglePlaneNbIdd <<= 1;
- *ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
- }
- IsPstateEnabled = TRUE;
- }
- return IsPstateEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns whether or not BIOS is responsible for configuring the NB COFVID.
- *
- * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PciAddress The northbridge to query by pci base address.
- * @param[out] NbVidUpdateAll Do all NbVids need to be updated
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE Perform northbridge frequency and voltage config.
- * @retval FALSE Do not configure them.
- */
-BOOLEAN
-F10CommonRevCGetNbCofVidUpdate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbVidUpdateAll,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ProductInfoRegister;
-
- PciAddress->Address.Register = PRCT_INFO_REG;
- PciAddress->Address.Function = FUNC_3;
- LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
- *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
- return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[in] NbPstate The NB P-state number to check.
- * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
- * @param[out] FreqDivisor The desired node's frequency divisor.
- * @param[out] VoltageInuV The desired node's voltage in microvolts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE NbPstate is valid
- * @retval FALSE NbPstate is disabled or invalid
- */
-BOOLEAN
-F10CommonRevCGetNbPstateInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- IN UINT32 NbPstate,
- OUT UINT32 *FreqNumeratorInMHz,
- OUT UINT32 *FreqDivisor,
- OUT UINT32 *VoltageInuV,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NbFid;
- UINT32 NbVid;
- UINT32 LocalPciRegister;
- UINT32 ProductInfoRegister;
- UINT64 LocalMsrRegister;
- BOOLEAN PstateIsValid;
-
- PstateIsValid = TRUE;
- if (NbPstate == 0) {
- *FreqDivisor = 1;
- } else if ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) {
- *FreqDivisor = 2;
- } else {
- PstateIsValid = FALSE;
- }
- if (PstateIsValid) {
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = PRCT_INFO_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
- if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
- PciAddress->Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
- NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
- LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
- NbVid = (UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid;
- } else {
- NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
- NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
- PciAddress->Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
- if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
- NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
- NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
- }
- }
- *FreqNumeratorInMHz = ((NbFid + 4) * 200);
- *VoltageInuV = (1550000 - (12500 * NbVid));
- }
- return PstateIsValid;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the node's minimum and maximum northbridge frequency.
- *
- * @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[out] MinFreqInMHz The node's miminum northbridge frequency.
- * @param[out] MaxFreqInMHz The node's maximum northbridge frequency.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_STATUS Northbridge frequency is valid
- */
-AGESA_STATUS
-F10RevCGetMinMaxNbFrequency (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- OUT UINT32 *MinFreqInMHz,
- OUT UINT32 *MaxFreqInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NbPstateEn;
- UINT32 NbFid;
- UINT32 FreqDivisor;
- UINT32 FreqNumerator;
- UINT32 LocalPciRegister;
- UINT32 ProductInfoRegister;
- CPU_LOGICAL_ID LogicalId;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
-
- FreqDivisor = 1;
-
- // If NB P-state is supported, return the frequency of NB P-state 1
- if ((PlatformConfig->PlatformProfile.PlatformPowerPolicy != Performance) &&
- ((LogicalId.Revision & AMD_F10_C3) != 0)) {
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = 0x1F0;
- LibAmdPciReadBits (*PciAddress, 18, 16, &NbPstateEn, StdHeader);
-
- if (NbPstateEn != 0) {
- FreqDivisor = 2;
- }
- }
-
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = PRCT_INFO_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
-
- if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
- PciAddress->Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
- NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
- } else {
- NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
- PciAddress->Address.Register = PW_CTL_MISC_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
- if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
- NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
- }
- }
-
- FreqNumerator = ((NbFid + 4) * 200);
- *MaxFreqInMHz = FreqNumerator;
- *MinFreqInMHz = (FreqNumerator / FreqDivisor);
-
- return AGESA_SUCCESS;
-
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is the Northbridge PState feature enabled?
- *
- * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE The NB PState feature is enabled.
- * @retval FALSE The NB PState feature is not enabled.
- */
-BOOLEAN
-F10CommonRevCIsNbPstateEnabled (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 NbPstate;
- PCI_ADDR PciAddress;
- CPU_LOGICAL_ID LogicalId;
- BOOLEAN Result;
-
- Result = FALSE;
-
- GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
- if (((LogicalId.Revision & AMD_F10_C3) != 0) && (!IsNonCoherentHt1 (StdHeader))) {
- OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = 0x1F0;
- LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
- if (NbPstate != 0) {
- Result = TRUE;
- }
- }
- return Result;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the number of physical cores of current processor.
- *
- * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The number of physical cores.
- */
-UINT8
-F10CommonRevCGetNumberOfPhysicalCores (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 LocalPciRegister;
- PCI_ADDR PciAddress;
-
- OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
- return (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo + 1);
-}
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c
deleted file mode 100644
index 9a9ea08..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c
+++ /dev/null
@@ -1,1039 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Microcode patch.
- *
- * Fam10 Microcode Patch rev 010000bf for 10a0 or equivalent.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/REVC
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "cpuEarlyInit.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// Patch code 010000bf for 10a0 and equivalent
-CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf =
-{{
-0x10,
-0x20,
-0x17,
-0x02,
-0xbf,
-0x00,
-0x00,
-0x01,
-0x00,
-0x80,
-0x20,
-0x00,
-0x42,
-0x82,
-0x02,
-0x39,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0x00,
-0xa0,
-0x10,
-0x00,
-0x00,
-0x00,
-0xaa,
-0xaa,
-0xaa,
-0x74,
-0x0f,
-0x00,
-0x00,
-0xbe,
-0x01,
-0x00,
-0x00,
-0x33,
-0x0e,
-0x00,
-0x00,
-0xa9,
-0x01,
-0x00,
-0x00,
-0x75,
-0x00,
-0x00,
-0x00,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xff,
-0xa0,
-0xfd,
-0xff,
-0x28,
-0xc3,
-0x3f,
-0xc0,
-0xcf,
-0xff,
-0x07,
-0xe2,
-0x01,
-0x0f,
-0xde,
-0x50,
-0xfe,
-0xf2,
-0xdf,
-0xff,
-0x0f,
-0x3b,
-0xfc,
-0x01,
-0xc5,
-0x40,
-0x03,
-0xd4,
-0x00,
-0x80,
-0xff,
-0xfe,
-0x7f,
-0xfe,
-0xe1,
-0x1b,
-0xc8,
-0x5b,
-0xf6,
-0xff,
-0xff,
-0x7b,
-0x87,
-0x5f,
-0xad,
-0x6b,
-0xf9,
-0x6f,
-0xfe,
-0xfa,
-0x1f,
-0xfe,
-0xb5,
-0x00,
-0x40,
-0x11,
-0x6a,
-0x0e,
-0xc0,
-0x9b,
-0x56,
-0xe8,
-0x75,
-0xe0,
-0x0f,
-0x38,
-0x00,
-0xcf,
-0xcc,
-0xa0,
-0xd7,
-0x83,
-0x3f,
-0xff,
-0x7b,
-0xfc,
-0xbf,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0x35,
-0x00,
-0x80,
-0xd0,
-0x18,
-0x07,
-0x60,
-0x19,
-0x07,
-0xf4,
-0x7a,
-0xf0,
-0xa6,
-0x1c,
-0x00,
-0x38,
-0x1f,
-0xc0,
-0xe7,
-0xa0,
-0xff,
-0xff,
-0x51,
-0x9e,
-0x7f,
-0x80,
-0x9f,
-0x87,
-0x80,
-0x0a,
-0x00,
-0x60,
-0xd3,
-0xe0,
-0x4f,
-0x10,
-0xfc,
-0x32,
-0xd8,
-0x3a,
-0x49,
-0xff,
-0x7f,
-0xcb,
-0xf0,
-0x0f,
-0xf0,
-0xf3,
-0x8c,
-0xff,
-0xff,
-0x00,
-0xc3,
-0x31,
-0x17,
-0xfd,
-0x2c,
-0x47,
-0x0d,
-0x00,
-0xd0,
-0x32,
-0xf0,
-0x27,
-0x1d,
-0x7e,
-0x19,
-0x6c,
-0x60,
-0xf1,
-0xff,
-0x1f,
-0x7f,
-0x38,
-0xe6,
-0xa2,
-0x16,
-0x35,
-0xff,
-0xff,
-0xe7,
-0xe1,
-0x1f,
-0xe0,
-0x00,
-0xfe,
-0xbf,
-0x07,
-0xbb,
-0x9c,
-0xf4,
-0xff,
-0x3f,
-0x0f,
-0xff,
-0x00,
-0x07,
-0xf8,
-0xdf,
-0x8d,
-0x0b,
-0x3e,
-0x78,
-0x73,
-0x3f,
-0x8b,
-0xff,
-0xff,
-0x70,
-0xe5,
-0xf0,
-0x0b,
-0x03,
-0x00,
-0x0f,
-0x50,
-0xff,
-0x52,
-0xfe,
-0xbb,
-0xaf,
-0xfa,
-0x87,
-0x7f,
-0xff,
-0x07,
-0xc0,
-0xff,
-0xa5,
-0x14,
-0x1f,
-0xbe,
-0xff,
-0x9f,
-0xc5,
-0xff,
-0xc4,
-0xaa,
-0x72,
-0xf8,
-0xef,
-0x01,
-0x80,
-0xff,
-0xeb,
-0xff,
-0x00,
-0x43,
-0x37,
-0x96,
-0xfd,
-0xc3,
-0xf6,
-0xff,
-0xab,
-0x80,
-0xff,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0xff,
-0x8f,
-0xe2,
-0xfc,
-0x02,
-0x54,
-0x39,
-0xda,
-0xd5,
-0x00,
-0x80,
-0xff,
-0x68,
-0x3c,
-0xe0,
-0xc1,
-0x9b,
-0xca,
-0xfe,
-0xe4,
-0xff,
-0xff,
-0x09,
-0x87,
-0x5f,
-0x06,
-0x5b,
-0xfe,
-0x0f,
-0xc4,
-0x03,
-0x1e,
-0xfa,
-0xa9,
-0x7c,
-0xe0,
-0xff,
-0x7b,
-0x00,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x00,
-0xf0,
-0xff,
-0x3d,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0x1e,
-0x00,
-0xf8,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x7f,
-0x0f,
-0x00,
-0xfc,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0xbf,
-0x07,
-0x00,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xfe,
-0x03,
-0xff,
-0xff,
-0x86,
-0x7f,
-0x00,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x01,
-0x80,
-0xff,
-0xef,
-0x7f,
-0xbf,
-0xff,
-0x81,
-0xdf,
-0x95,
-0xc1,
-0xaf,
-0xff,
-0x91,
-0xfc,
-0x2f,
-0x48,
-0x57,
-0x06,
-0xbf,
-0xff,
-0x4f,
-0xb0,
-0xff,
-0x32,
-0xd8,
-0x3a,
-0xfc,
-0xd7,
-0x00,
-0x40,
-0x95,
-0x81,
-0xff,
-0x94,
-0x01,
-0x1f,
-0xe0,
-0xe7,
-0xe1,
-0xff,
-0xff,
-0x53,
-0xce,
-0x7f,
-0xa9,
-0xeb,
-0x83,
-0xff,
-0xef,
-0x4b,
-0xfd,
-0xfc,
-0xbd,
-0xbd,
-0x0e,
-0xff,
-0x7b,
-0x00,
-0xe0,
-0x9c,
-0x56,
-0x0e,
-0x00,
-0xd0,
-0x0f,
-0xe0,
-0x73,
-0xff,
-0x81,
-0x7f,
-0x00,
-0xc3,
-0x3f,
-0x80,
-0x7f,
-0xfc,
-0x07,
-0xfe,
-0x01,
-0x0d,
-0xff,
-0x00,
-0xfe,
-0xe0,
-0xfd,
-0x35,
-0x00,
-0xe0,
-0x0d,
-0x2b,
-0x07,
-0x3a,
-0xf0,
-0x07,
-0xf4,
-0x96,
-0xff,
-0xed,
-0x3f,
-0xff,
-0xe1,
-0x1f,
-0xab,
-0x5b,
-0x02,
-0x00,
-0xfe,
-0xfb,
-0x87,
-0x7f,
-0xac,
-0x00,
-0xa8,
-0xcd,
-0x1a,
-0x6f,
-0x72,
-0xc0,
-0xff,
-0xfc,
-0x3c,
-0xfc,
-0x03,
-0x1f,
-0xc0,
-0x7f,
-0xe0,
-0xe0,
-0xdf,
-0xf0,
-0x0f,
-0x7f,
-0x00,
-0xff,
-0x81,
-0x80,
-0x7f,
-0xc3,
-0x3f,
-0x0f,
-0x00,
-0xfc,
-0x7f,
-0xff,
-0x7f,
-0x79,
-0xfc,
-0x01,
-0x7e,
-0x1e,
-0xfe,
-0x2b,
-0x07,
-0xe0,
-0xfe,
-0x07,
-0xf0,
-0x39,
-0xe8,
-0xc0,
-0x3f,
-0x80,
-0xff,
-0x1f,
-0xc0,
-0xbf,
-0xe1,
-0xb9,
-0x06,
-0x00,
-0x78,
-0xf6,
-0xff,
-0xbf,
-0x80,
-0xff,
-0x00,
-0x3f,
-0x0f,
-0xff,
-0xff,
-0x8f,
-0xe2,
-0xfc,
-0x03,
-0xfc,
-0x3c,
-0x7f,
-0x34,
-0x1e,
-0xf0,
-0xd0,
-0xef,
-0xe5,
-0xf3,
-0xff,
-0xdf,
-0x03,
-0x00,
-0xee,
-0xa3,
-0x72,
-0x00,
-0x83,
-0x7e,
-0x00,
-0x9f,
-0xf8,
-0xfd,
-0xff,
-0x07,
-0x1f,
-0xbe,
-0xb1,
-0xec,
-0x65,
-0x97,
-0xff,
-0x1f,
-0x79,
-0xf8,
-0x07,
-0xf8,
-0x80,
-0xc4,
-0x97,
-0x01,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x01,
-0xfc,
-0x07,
-0xfe,
-0xfe,
-0x0d,
-0xff,
-0x00,
-0x07,
-0xf0,
-0x1f,
-0xf8,
-0xf8,
-0x37,
-0xfc,
-0x03,
-0x00,
-0xc0,
-0xff,
-0xf7,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0xff,
-0x00,
-0xfe,
-0x03,
-0x00,
-0xff,
-0x86,
-0x7f,
-0xfc,
-0x03,
-0xf8,
-0x0f,
-0x01,
-0xfc,
-0x1b,
-0xfe,
-0x7b,
-0x00,
-0xe0,
-0xff,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0x81,
-0x7f,
-0x00,
-0xff,
-0x3f,
-0x80,
-0x7f,
-0xc3,
-0x07,
-0xfe,
-0x01,
-0xfc,
-0xff,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0x3d,
-0x00,
-0xf0,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xc0,
-0x3f,
-0x80,
-0xe1,
-0x1f,
-0xc0,
-0xbf,
-0xfe,
-0x03,
-0xff,
-0x00,
-0x86,
-0x7f,
-0x00,
-0xff,
-0xf8,
-0xff,
-0x1e,
-0x00,
-0xf0,
-0x1f,
-0xf8,
-0x07,
-0x37,
-0xfc,
-0x03,
-0xf8,
-0xc0,
-0x7f,
-0xe0,
-0x1f,
-0xdf,
-0xf0,
-0x0f,
-0xe0,
-0x00,
-0xff,
-0x81,
-0x7f,
-0x7f,
-0xc3,
-0x3f,
-0x80,
-0x00,
-0xfc,
-0x7f,
-0x0f,
-0x03,
-0xf8,
-0x0f,
-0xfc,
-0xfc,
-0x1b,
-0xfe,
-0x01,
-0x0f,
-0xe0,
-0x3f,
-0xf0,
-0xf0,
-0x6f,
-0xf8,
-0x07,
-0x3f,
-0x80,
-0xff,
-0xc0,
-0xc0,
-0xbf,
-0xe1,
-0x1f,
-0x07,
-0x00,
-0xfe,
-0xbf,
-0xfe,
-0x01,
-0xfc,
-0x07,
-0x00,
-0xfe,
-0x0d,
-0xff,
-0xf8,
-0x07,
-0xf0,
-0x1f,
-0x03,
-0xf8,
-0x37,
-0xfc,
-0xe0,
-0x1f,
-0xc0,
-0x7f,
-0x0f,
-0xe0,
-0xdf,
-0xf0,
-0xdf,
-0x03,
-0x00,
-0xff,
-0x03,
-0xff,
-0x00,
-0xfe,
-0x7f,
-0x00,
-0xff,
-0x86,
-0x0f,
-0xfc,
-0x03,
-0xf8,
-0xfe,
-0x01,
-0xfc,
-0x1b,
-0x3f,
-0xf0,
-0x0f,
-0xe0,
-0xf8,
-0x07,
-0xf0,
-0x6f,
-0xff,
-0xef,
-0x01,
-0x80
-}};
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c
deleted file mode 100644
index 52630d9..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c
+++ /dev/null
@@ -1,373 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev E HT PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// HT Phy T a b l e s
-// -------------------------
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEHtPhyRegisters[] =
-{
-// 0x60:0x68
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x60, 0x68, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }}
- },
-// 0x70:0x78
- {
- HtPhyRangeRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x70, 0x78, // Address range
- 0x00000040, // regData
- 0x00000040, // regMask
- }}
- },
-// 0xC0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL0_ALL, //
- 0xC0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }}
- },
-// 0xD0
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL1_ALL, //
- 0xD0, // Address
- 0x40040000, // regData
- 0xe01F0000, // regMask
- }}
- },
-// 0x520A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL0_ALL, //
- 0x520A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }}
- },
-// 0x530A
- {
- HtPhyRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- HTPHY_LINKTYPE_SL1_ALL, //
- 0x530A, // Address
- 0x00004000, // regData
- 0x00006000, // regMask
- }}
- },
-
-
-//
-// Deemphasis Settings
-//
-
-// For C3, also set [7]TxLs23ClkGateEn.
-//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
-// No deemphasis 00h 00h 00h 0 0 0 0
-// -3dB postcursor 12h 00h 00h 1 0 0 0
-// -6dB postcursor 1Fh 00h 00h 1 0 0 0
-// -8dB postcursor 1Fh 06h 00h 1 1 0 1
-// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
-// -11dB postcursor with
-// -8dB precursor 1Fh 06h 07h 1 1 1 1
-
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL_NONE,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x00000080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__3,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x80120080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__6,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0x801F0080, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F06C0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xC01F0DC0, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL0_HT3, //
- 0xC5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }}
- },
- {
- DeemphasisRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- DEEMPHASIS_LEVEL__11_8,
- HTPHY_LINKTYPE_SL1_HT3, //
- 0xD5, // Address
- 0xE01F06C7, // regData
- 0xE01F1FDF, // regMask
- }}
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevEHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevEHtPhyRegisters
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c
deleted file mode 100644
index 59cce83..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev E, MSR tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevEMsrRegisters[] =
-{
-// M S R T a b l e s
-// ----------------------
-// MSR_LS_CFG (0xC0011020)
-// bit[1] = 0
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MSR_LS_CFG, // MSR Address
- 0x0000000000000000, // OR Mask
- (1 << 1), // NAND Mask
- }}
- },
-
-// MSR_BU_CFG (0xC0011023)
-// bit[21] = 1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MSR_BU_CFG, // MSR Address
- (1 << 21), // OR Mask
- (1 << 21), // NAND Mask
- }}
- },
-
-// MSR_BU_CFG2 (0xC001102A)
-// bit[50] = 1
-// For GH rev C1 and later [RdMmExtCfgQwEn]=1
- {
- MsrRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MSR_BU_CFG2, // MSR Address
- 0x0004000000000000, // OR Mask
- 0x0004000000000000, // NAND Mask
- }}
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable = {
- AllCores,
- (sizeof (F10RevEMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- (TABLE_ENTRY_FIELDS *) &F10RevEMsrRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c
deleted file mode 100644
index ab5e1fe..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 Rev E PCI tables with values as defined in BKDG
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/FAMILY/0x10/RevE
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "cpuRegisters.h"
-#include "Table.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-// P C I T a b l e s
-// ----------------------
-
-STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEPciRegisters[] =
-{
-// F0x68 -
-// BufRelPri for rev E
-// bits[14:13] BufRelPri = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address
- 0x00002000, // regData
- 0x00006000, // regMask
- }}
- },
-
-// F0x16C - Link Global Extended Control Register
-// bit[7:6] InLnSt = 0x01
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_SINGLE_LINK}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C026, // regData
- 0x0000E03F, // regMask
- }}
- },
-// F0x16C - Link Global Extended Control Register
-// bit[15:13] ForceFullT0 = 6
-// bit[9] RXCalEn = 1
-// bit[5:0] T0Time = 0x26
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_SINGLE_LINK}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
- 0x0000C226, // regData
- 0x0000E23F, // regMask
- }}
- },
-// F3x80 - ACPI Power State Control
-// ACPI State C2
-// bits[0] CpuPrbEn = 1
-// bits[1] NbLowPwrEn = 0
-// bits[2] NbGateEn = 0
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 1
-// ACPI State C3, C1E or Link init
-// bits[0] CpuPrbEn = 0
-// bits[1] NbLowPwrEn = 1
-// bits[2] NbGateEn = 1
-// bits[3] NbCofChg = 0
-// bits[4] AltVidEn = 0
-// bits[7:5] ClkDivisor = 7
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
- 0x0000E681, // regData
- 0x0000FFFF, // regMask
- }}
- },
-// F3xDC - Clock Power Timing Control 2
-// bits[14:12] NbsynPtrAdj = 6
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
- 0x00006000, // regData
- 0x00007000, // regMask
- }}
- },
-// F3x1C4 - L3 Power Control Register
-// bits[8] L3PwrSavEn = 1
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
- 0x00000100, // regData
- 0x00000100, // regMask
- }}
- },
-// F3x188 - NB Extended Configuration Low Register
-// bit[4] = EnStpGntOnFlushMaskWakeup
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
- 0x00000010, // regData
- 0x00000010, // regMask
- }}
- },
-// F4x15C - Core Performance Boost Control
-// bits[1:0] BoostSrc = 0
- {
- PciRegister,
- {
- AMD_FAMILY_10, // CpuFamily
- AMD_F10_Ex // CpuRevision
- },
- {AMD_PF_ALL}, // platformFeatures
- {{
- MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
- 0x00000000, // regData
- 0x00000003, // regMask
- }}
- },
-};
-
-CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable = {
- PrimaryCores,
- (sizeof (F10RevEPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
- F10RevEPciRegisters,
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
deleted file mode 100644
index 476ae27..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Family_10 revision Ex specific utility functions.
- *
- * Provides numerous utility functions specific to family 10h rev E.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU/F10
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- */
-/*
- ******************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include "AGESA.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "cpuRegisters.h"
-#include "cpuFamilyTranslation.h"
-#include "cpuF10PowerMgmt.h"
-#include "GeneralServices.h"
-#include "cpuEarlyInit.h"
-#include "cpuRegisters.h"
-#include "OptionMultiSocket.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Set down core register on a revision E processor.
- *
- * This function set F3x190 Downcore Control Register[5:0]
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket Socket ID.
- * @param[in] Module Module ID in socket.
- * @param[in] LeveledCores Number of core.
- * @param[in] CoreLevelMode Core level mode.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Down Core register is updated.
- * @retval FALSE Down Core register is not updated.
- */
-BOOLEAN
-F10CommonRevESetDownCoreRegister (
- IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT32 *Socket,
- IN UINT32 *Module,
- IN UINT32 *LeveledCores,
- IN CORE_LEVELING_TYPE CoreLevelMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 TempVar32_a;
- UINT32 CoreDisableBits;
- PCI_ADDR PciAddress;
- BOOLEAN IsUpdated;
- AGESA_STATUS AgesaStatus;
-
- IsUpdated = FALSE;
-
- switch (*LeveledCores) {
- case 1:
- CoreDisableBits = DOWNCORE_MASK_SINGLE;
- break;
- case 2:
- CoreDisableBits = DOWNCORE_MASK_DUAL;
- break;
- case 3:
- CoreDisableBits = DOWNCORE_MASK_TRI;
- break;
- case 4:
- CoreDisableBits = DOWNCORE_MASK_FOUR;
- break;
- case 5:
- CoreDisableBits = DOWNCORE_MASK_FIVE;
- break;
- default:
- CoreDisableBits = 0;
- break;
- }
-
- if (CoreDisableBits != 0) {
- if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
-
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
- if (TempVar32_a == 0) {
- CoreDisableBits &= 0x1;
- } else if (TempVar32_a == 1) {
- CoreDisableBits &= 0x3;
- } else if (TempVar32_a == 2) {
- CoreDisableBits &= 0x7;
- } else if (TempVar32_a == 3) {
- CoreDisableBits &= 0x0F;
- } else if (TempVar32_a == 4) {
- CoreDisableBits &= 0x1F;
- } else if (TempVar32_a == 5) {
- CoreDisableBits &= 0x3F;
- }
- PciAddress.Address.Register = DOWNCORE_CTRL;
- LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
- TempVar32_a |= CoreDisableBits;
- LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
- IsUpdated = TRUE;
- }
- }
- }
-
- return IsUpdated;
-}
-
-
-CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling =
-{
- 0,
- F10CommonRevESetDownCoreRegister
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get CPU pstate current on a revision E processor.
- *
- * @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
- *
- * This function returns the ProcIddMax.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Pstate The P-state to check.
- * @param[out] ProcIddMax P-state current in mA.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE P-state is enabled
- * @retval FALSE P-state is disabled
- */
-BOOLEAN
-F10CommonRevEGetProcIddMax (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN UINT8 Pstate,
- OUT UINT32 *ProcIddMax,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 IddDiv;
- UINT32 CmpCap;
- UINT32 LocalPciRegister;
- UINT32 MsrAddress;
- UINT32 MultiNodeCpu;
- UINT64 PstateMsr;
- BOOLEAN IsPstateEnabled;
- PCI_ADDR PciAddress;
-
- IsPstateEnabled = FALSE;
-
- MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
- ASSERT (MsrAddress <= PS_MAX_REG);
-
- LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
- if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
- OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
-
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
-
- switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
- case 0:
- IddDiv = 1000;
- break;
- case 1:
- IddDiv = 100;
- break;
- case 2:
- IddDiv = 10;
- break;
- default: // IddDiv = 3 is reserved. Use 10
- ASSERT (FALSE);
- IddDiv = 10;
- break;
- }
- MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->MultiNodeCpu + 1);
- CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapHi << 2);
- CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
- CmpCap++;
- *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
- IsPstateEnabled = TRUE;
- }
- return IsPstateEnabled;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Determines the NB clock on the desired node.
- *
- * @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[in] NbPstate The NB P-state number to check.
- * @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
- * @param[out] FreqDivisor The desired node's frequency divisor.
- * @param[out] VoltageInuV The desired node's voltage in microvolts.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval TRUE NbPstate is valid
- * @retval FALSE NbPstate is disabled or invalid
- */
-BOOLEAN
-F10CommonRevEGetNbPstateInfo (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- IN UINT32 NbPstate,
- OUT UINT32 *FreqNumeratorInMHz,
- OUT UINT32 *FreqDivisor,
- OUT UINT32 *VoltageInuV,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 LocalPciRegister;
- UINT64 LocalMsrRegister;
- BOOLEAN PstateIsValid;
-
- PstateIsValid = FALSE;
- if (NbPstate == 0) {
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
- *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
- *FreqDivisor = 1;
- LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
- *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid)));
- PstateIsValid = TRUE;
- }
- return PstateIsValid;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns the node's minimum and maximum northbridge frequency.
- *
- * @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PlatformConfig Platform profile/build option config structure.
- * @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
- * @param[out] MinFreqInMHz The node's minimum northbridge frequency.
- * @param[out] MaxFreqInMHz The node's maximum northbridge frequency.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @retval AGESA_STATUS Northbridge frequency is valid
- */
-AGESA_STATUS
-F10RevEGetMinMaxNbFrequency (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN PCI_ADDR *PciAddress,
- OUT UINT32 *MinFreqInMHz,
- OUT UINT32 *MaxFreqInMHz,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 LocalPciRegister;
-
- PciAddress->Address.Function = FUNC_3;
- PciAddress->Address.Register = CPTC0_REG;
- LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
- *MinFreqInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
- *MaxFreqInMHz = *MinFreqInMHz;
-
- return AGESA_SUCCESS;
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Returns whether or not BIOS is responsible for configuring the NB COFVID.
- *
- * @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] PciAddress The northbridge to query by pci base address.
- * @param[out] NbVidUpdateAll Do all NbVids need to be updated
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE Perform northbridge frequency and voltage config.
- * @retval FALSE Do not configure them.
- */
-BOOLEAN
-F10CommonRevEGetNbCofVidUpdate (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN PCI_ADDR *PciAddress,
- OUT BOOLEAN *NbVidUpdateAll,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 ProductInfoRegister;
-
- PciAddress->Address.Register = PRCT_INFO_REG;
- PciAddress->Address.Function = FUNC_3;
- LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
- *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
- return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
-}
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Get the number of physical cores of current processor.
- *
- * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] StdHeader Handle of Header for calling lib functions and services.
- *
- * @return The number of physical cores.
- */
-UINT8
-F10CommonRevEGetNumberOfPhysicalCores (
- IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
- IN AMD_CONFIG_PARAMS *StdHeader
- )
-{
- UINT32 CmpCap;
- UINT32 LocalPciRegister;
- PCI_ADDR PciAddress;
-
- OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
- PciAddress.Address.Function = FUNC_3;
- PciAddress.Address.Register = NB_CAPS_REG;
- LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
- CmpCap = (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapHi << 2);
- CmpCap |= (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
-
- return (UINT8) (CmpCap + 1);
-}
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c
deleted file mode 100644
index 8f522b9..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpSorA3.c
- *
- * Platform specific settings for OR AM3 DDR3 SO-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps/OR/AM3)
- * @e \$Revision: 50871 $ @e \$Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "mu.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-// Slow mode, Address timing and Output drive compensation
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC
-//
-STATIC CONST PSCFG_SAO_ENTRY OrAM3SODdr3SAO[] = {
- {1, DDR667 + DDR800, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222},
- {1, DDR667 + DDR800, V1_5, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222},
- {1, DDR1066, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222},
- {1, DDR1066, V1_5, DIMM_DR, NP, NP, 0, 0x00380000, 0x10112222},
- {1, DDR1333, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x20112222},
- {1, DDR1333, V1_5, DIMM_DR, NP, NP, 0, 0x00360000, 0x20112222},
- {1, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x30112222},
- {1, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00000000, 0x30112222},
- {2, DDR667 + DDR800, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222},
- {2, DDR667 + DDR800, V1_5, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222},
- {2, DDR667, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222322},
- {2, DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222322},
- {2, DDR1066, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222},
- {2, DDR1066, V1_5, NP, DIMM_DR, NP, 0, 0x00380000, 0x10112222},
- {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00350037, 0x30222322},
- {2, DDR1333, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x20112222},
- {2, DDR1333, V1_5, NP, DIMM_DR, NP, 0, 0x00360000, 0x20112222},
- {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000035, 0x30222322},
- {2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x30112222},
- {2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00000000, 0x30112222},
- {2, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000033, 0x30222322}
-};
-CONST PSC_TBL_ENTRY SAOTblEntSOAM3 = {
- {PSCFG_SAO, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (OrAM3SODdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
- (VOID *)&OrAM3SODdr3SAO
-};
-// training configuratrions
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D
-//
-STATIC CONST PSCFG_S___ENTRY OrAM3SODdr3S__[] = {
- {1, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0},
- };
-CONST PSC_TBL_ENTRY S__TblEntSOAM3 = {
- {PSCFG_S__, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (OrAM3SODdr3S__) / sizeof (PSCFG_S___ENTRY),
- (VOID *)&OrAM3SODdr3S__
-};
-// ODT pattern for 1 DPC
-// Format:
-// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
-//
-STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1SODdr3OdtPat[] = {
- {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001},
- {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}
-};
-CONST PSC_TBL_ENTRY OdtPat1DTblEntSOAM3 = {
- {PSCFG_ODT_PAT_1D, SODIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (Or1SODdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY),
- (VOID *)&Or1SODdr3OdtPat
-};
-
-// ODT pattern for 2 DPC
-// Format:
-// Dimm0, Dimm1, ,RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
-//
-STATIC CONST PSCFG____ODTPAT_ENTRY Or2SODdr3OdtPat[] = {
- {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000},
- {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000},
- {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}
-};
-CONST PSC_TBL_ENTRY OdtPat2DTblEntSOAM3 = {
- {PSCFG_ODT_PAT___, SODIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (Or2SODdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY),
- (VOID *)&Or2SODdr3OdtPat
-};
-
-// ODT pattern for 3 DPC
-// Format:
-// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
-//
-STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3SODdr3OdtPat[] = {
- {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000404, 0x00000000},
- {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405}
-};
-CONST PSC_TBL_ENTRY OdtPat3DTblEntSOAM3 = {
- {PSCFG_ODT_PAT_3D, SODIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (Or3SODdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY),
- (VOID *)&Or3SODdr3OdtPat
-};
-
-// Dram Term and Dynamic Dram Term
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
-//
-STATIC CONST PSCFG_RTT_ENTRY DramTermOrAM3SODIMM[] = {
- {1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0},
- {1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0},
- {1, DDR1333, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0},
- {1, DDR1333, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0},
- {1, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0},
- {1, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0},
- {2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0},
- {2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
- {2, DDR1333, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0},
- {2, DDR1333, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0},
- {2, DDR1333, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2},
- {2, DDR1333, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
- {2, DDR1333, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2},
- {2, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
- {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
- {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}
-};
-CONST PSC_TBL_ENTRY DramTermTblEntSOAM3 = {
- {PSCFG_RTT, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (DramTermOrAM3SODIMM) / sizeof (PSCFG_RTT_ENTRY),
- (VOID *)&DramTermOrAM3SODIMM
-};
-
-// Max Freq.
-// Format :
-// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
-//
-STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrAM3SODIMM[] = {
- {1, 1, 1, 0, 0, DDR1866_FREQUENCY, 0, 0},
- {1, 1, 0, 1, 0, DDR1866_FREQUENCY, 0, 0},
- {2, 1, 1, 0, 0, DDR1600_FREQUENCY, 0, 0},
- {2, 1, 0, 1, 0, DDR1600_FREQUENCY, 0, 0},
- {2, 2, 2, 0, 0, DDR1600_FREQUENCY, 0, 0},
- {2, 2, 1, 1, 0, DDR1333_FREQUENCY, 0, 0},
- {2, 2, 0, 2, 0, DDR1333_FREQUENCY, 0, 0}
-};
-CONST PSC_TBL_ENTRY MaxFreqTblEntSOAM3 = {
- {PSCFG_MAXFREQ, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (MaxFreqOrAM3SODIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
- (VOID *)&MaxFreqOrAM3SODIMM
-};
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpUorA3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpUorA3.c
deleted file mode 100644
index e14c7b6..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpUorA3.c
+++ /dev/null
@@ -1,278 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mpUorA3.c
- *
- * Platform specific settings for OR AM3 DDR3 U-DIMM system
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Ps/OR/AM3)
- * @e \$Revision: 55134 $ @e \$Date: 2011-06-16 15:27:02 -0600 (Thu, 16 Jun 2011) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "PlatformMemoryConfiguration.h"
-#include "ma.h"
-#include "Ids.h"
-#include "cpuFamRegisters.h"
-#include "cpuRegisters.h"
-#include "mm.h"
-#include "mn.h"
-#include "mp.h"
-#include "Filecode.h"
-CODE_GROUP (G2_PEI)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/*
- *-----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *-----------------------------------------------------------------------------
- */
-// Slow mode, Address timing and Output drive compensation
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC
-//
-STATIC CONST PSCFG_SAO_ENTRY OrAM3UDdr3SAO[] = {
- {1, DDR667 + DDR800, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222},
- {1, DDR667 + DDR800, V1_5, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222},
- {1, DDR1066, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222},
- {1, DDR1066, V1_5, DIMM_DR, NP, NP, 0, 0x00380000, 0x10112222},
- {1, DDR1333, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x20112222},
- {1, DDR1333, V1_5, DIMM_DR, NP, NP, 0, 0x00360000, 0x20112222},
- {1, DDR1600, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x30112222},
- {1, DDR1600, V1_5, DIMM_DR, NP, NP, 1, 0x00000000, 0x30112222},
- {1, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x30332222},
- {1, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00000000, 0x30332222},
- {2, DDR667 + DDR800, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222},
- {2, DDR667 + DDR800, V1_5, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222},
- {2, DDR667, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222322},
- {2, DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222322},
- {2, DDR1066, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222},
- {2, DDR1066, V1_5, NP, DIMM_DR, NP, 0, 0x00380000, 0x10112222},
- {2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00350037, 0x30222322},
- {2, DDR1333, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x20112222},
- {2, DDR1333, V1_5, NP, DIMM_DR, NP, 0, 0x00360000, 0x20112222},
- {2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000035, 0x30222322},
- {2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x30112222},
- {2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00000000, 0x30112222},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 1, 0x00000033, 0x30222322},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 1, 0x00000033, 0x30222322},
- {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000033, 0x30222322},
- {2, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x30332222},
- {2, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00000000, 0x30332222},
-};
-CONST PSC_TBL_ENTRY SAOTblEntUAM3 = {
- {PSCFG_SAO, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (OrAM3UDdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
- (VOID *)&OrAM3UDdr3SAO
-};
-// training configuratrions
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D
-//
-STATIC CONST PSCFG_S___ENTRY OrAM3UDdr3S__[] = {
- // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training
- {1, DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600 + DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0},
- // DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training
- {2, DDR667 + DDR800 + DDR1066 + DDR1333, V1_5, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0},
- {2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 0},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 0},
- {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0},
- {2, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0}, };
-CONST PSC_TBL_ENTRY S__TblEntUAM3 = {
- {PSCFG_S__, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (OrAM3UDdr3S__) / sizeof (PSCFG_S___ENTRY),
- (VOID *)&OrAM3UDdr3S__
-};
-// ODT pattern for 1 DPC
-// Format:
-// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
-//
-STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1UDdr3OdtPat[] = {
- {DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001},
- {DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}
-};
-CONST PSC_TBL_ENTRY OdtPat1DTblEntUAM3 = {
- {PSCFG_ODT_PAT_1D, UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (Or1UDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY),
- (VOID *)&Or1UDdr3OdtPat
-};
-
-// ODT pattern for 2 DPC
-// Format:
-// Dimm0, Dimm1, ,RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
-//
-STATIC CONST PSCFG____ODTPAT_ENTRY Or2UDdr3OdtPat[] = {
- {NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000},
- {NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000},
- {DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}
-};
-CONST PSC_TBL_ENTRY OdtPat2DTblEntUAM3 = {
- {PSCFG_ODT_PAT___, UDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (Or2UDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY),
- (VOID *)&Or2UDdr3OdtPat
-};
-
-// ODT pattern for 3 DPC
-// Format:
-// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
-//
-STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3UDdr3OdtPat[] = {
- {NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000},
- {DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405}
-};
-CONST PSC_TBL_ENTRY OdtPat3DTblEntUAM3 = {
- {PSCFG_ODT_PAT_3D, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (Or3UDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY),
- (VOID *)&Or3UDdr3OdtPat
-};
-
-// Dram Term and Dynamic Dram Term
-// Format :
-// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
-//
-STATIC CONST PSCFG_RTT_ENTRY DramTermOrAM3UDIMM[] = {
- {1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0},
- {1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0},
- {1, DDR1333, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0},
- {1, DDR1333, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0},
- {1, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0},
- {1, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0},
- {2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0},
- {2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
- {2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
- {2, DDR1333, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0},
- {2, DDR1333, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0},
- {2, DDR1333, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2},
- {2, DDR1333, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
- {2, DDR1333, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2},
- {2, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
- {2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0},
- {2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 4, 1},
- {2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1},
- {2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 4, 1},
- {2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1},
- {2, DDR1866, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0},
- {2, DDR1866, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0},
-};
-CONST PSC_TBL_ENTRY DramTermTblEntUAM3 = {
- {PSCFG_RTT, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (DramTermOrAM3UDIMM) / sizeof (PSCFG_RTT_ENTRY),
- (VOID *)&DramTermOrAM3UDIMM
-};
-
-// Max Freq.
-// Format :
-// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
-//
-STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrAM3UDIMM[] = {
- {1, 1, 1, 0, 0, DDR1866_FREQUENCY, 0, 0},
- {1, 1, 0, 1, 0, DDR1866_FREQUENCY, 0, 0},
- {2, 1, 1, 0, 0, DDR1600_FREQUENCY, 0, 0},
- {2, 1, 0, 1, 0, DDR1600_FREQUENCY, 0, 0},
- {2, 2, 2, 0, 0, DDR1600_FREQUENCY, 0, 0},
- {2, 2, 1, 1, 0, DDR1333_FREQUENCY, 0, 0},
- {2, 2, 0, 2, 0, DDR1333_FREQUENCY, 0, 0}
-};
-CONST PSC_TBL_ENTRY MaxFreqTblEntUAM3 = {
- {PSCFG_MAXFREQ, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (MaxFreqOrAM3UDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
- (VOID *)&MaxFreqOrAM3UDIMM
-};
-
-//
-// MemClkDis
-//
-STATIC CONST UINT8 ROMDATA OrUDdr3CLKDis[] = {0x02, 0x01, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00};
-CONST PSC_TBL_ENTRY ClkDisMapEntUAM3 = {
- {PSCFG_CLKDIS, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (OrUDdr3CLKDis) / sizeof (UINT8),
- (VOID *)&OrUDdr3CLKDis
-};
-
-//
-// WL pass1 seed
-//
-// Format :
-// DimmPerCh in bit map, Channel #, Seed value
-STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrAM3UDIMM[] = {
- {_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x0F}
-};
-CONST PSC_TBL_ENTRY WLPass1SeedEntUAM3 = {
- {PSCFG_WL_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (WLPas1SeedOrAM3UDIMM) / sizeof (PSCFG_SEED_ENTRY),
- (VOID *)&WLPas1SeedOrAM3UDIMM
-};
-
-//
-// HW RxEn pass1 seed
-//
-// Format :
-// DimmPerCh in bit map, Channel #, Seed value
-STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrAM3UDIMM[] = {
- {_1DIMM + _2DIMM, CH_A + CH_B, 0x3A},
-};
-CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntUAM3 = {
- {PSCFG_HWRXEN_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
- sizeof (HWRxEnPas1SeedOrAM3UDIMM) / sizeof (PSCFG_SEED_ENTRY),
- (VOID *)&HWRxEnPas1SeedOrAM3UDIMM
-};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
deleted file mode 100644
index f2a5bc4..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt2.c
- *
- * Common Technology functions for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (C) 2012 Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "Ids.h"
-#include "AdvancedApi.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mt2.h"
-#include "mtspd2.h"
-#include "mtot2.h"
-#include "OptionMemory.h"
-#include "PlatformMemoryConfiguration.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-/* features */
-#include "mftds.h"
-#define FILECODE PROC_MEM_TECH_DDR2_MT2_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function Constructs the technology block
- *
- * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-BOOLEAN
-MemConstructTechBlock2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- )
-{
- TECHNOLOGY_TYPE *TechTypePtr;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- UINT8 DimmSlots;
-
- TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0, 0, NULL, NULL);
- if (TechTypePtr != NULL) {
- // Ensure the platform override value is valid
- ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
- if (*TechTypePtr != DDR2_TECHNOLOGY) {
- return FALSE;
- }
- }
-
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- TechPtr->NBPtr = NBPtr;
- TechPtr->RefPtr = NBPtr->RefPtr;
-
- TechPtr->SetDramMode = MemTSetDramMode2;
- TechPtr->DimmPresence = MemTDIMMPresence2;
- TechPtr->SpdCalcWidth = MemTSPDCalcWidth2;
- TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed2;
- TechPtr->AutoCycTiming = MemTAutoCycTiming2;
- TechPtr->SpdSetBanks = MemTSPDSetBanks2;
- TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
- TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr2;
- TechPtr->AdjustTwrwr = MemTAdjustTwrwr2;
- TechPtr->AdjustTwrrd = MemTAdjustTwrrd2;
- TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer2;
- TechPtr->GetLD = MemTGetLD2;
- TechPtr->MaxFilterDly = 0;
-
- //
- // Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
- // The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
- //
- // DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
- // (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
- // on this array only)
- // 2 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // DimmSpdPtr[2]------->NULL
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // | DimmSpdPtr[2]------->NULL
- // +----DimmSpdPtr[3]
- //
- // Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
- // +-- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- // 3 DIMMS PER CHANNEL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
- // DimmSpdPtr[3]------->NULL
- //
- // Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
- // Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
- // Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
- // +----DimmSpdPtr[3]
- //
- //
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->TechType = DDR2_TECHNOLOGY;
- ChannelPtr->MCTPtr = MCTPtr;
- ChannelPtr->DCTPtr = DCTPtr;
-
- DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- //
- // Initialize the SPD pointers for each Dimm
- //
- for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
- ChannelPtr->DimmSpdPtr[i] = NULL;
- }
- for (i = 0 ; i < DimmSlots; i++) {
- ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
- if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
- if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
- if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_DM_BANKS] >> 3) & 0x07) + 1) > 2) {
- ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
- }
- }
- }
- }
- }
- }
- return TRUE;
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h
deleted file mode 100644
index 54cac5d..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mt2.h
- *
- * Common Technology
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MT2_H_
-#define _MT2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-BOOLEAN
-MemConstructTechBlock2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT MEM_NB_BLOCK *NBPtr
- );
-
-BOOLEAN
-MemTSetDramMode2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTDIMMPresence2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDCalcWidth2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDGetTargetSpeed2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTAutoCycTiming2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-MemTSPDSetBanks2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTGetCSIntLvAddr2 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- );
-
-BOOLEAN
-MemTGetDimmSpdBuffer2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- );
-
-#endif /* _MT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
deleted file mode 100644
index 8d4503b..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot2.c
- *
- * Technology Non-SPD Timings for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (C) 2012 Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "mm.h"
-#include "mn.h"
-#include "mu.h"
-#include "mt.h"
-#include "mtot2.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_TECH_DDR2_MTOT2_FILECODE
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrwr value for DDR2.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrwr2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR2, 1 clock has encoded value of 0.
- // Need to transfer clk value to encoded value.
- if (DCTPtr->Timings.Twrwr >= 1) {
- DCTPtr->Timings.Twrwr -= 1;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function adjusts the Twrrd value for DDR2.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- */
-
-VOID
-MemTAdjustTwrrd2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- DCT_STRUCT *DCTPtr;
-
- DCTPtr = TechPtr->NBPtr->DCTPtr;
-
- // For DDR2, 1 clock has encoded value of 0.
- // Need to transfer clk value to encoded value.
- if (DCTPtr->Timings.Twrrd >= 1) {
- DCTPtr->Timings.Twrrd -= 1;
- }
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function gets the LD value for DDR2
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return value of LD
- */
-
-INT8
-MemTGetLD2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- INT8 LD;
-
- // For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
- LD = 1;
-
- return LD;
-}
-
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h
deleted file mode 100644
index 2dda044..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtot2.h
- *
- * Technology Non-SPD timings for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTOT2_H_
-#define _MTOT2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-VOID
-MemTAdjustTwrwr2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-VOID
-MemTAdjustTwrrd2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-INT8
-MemTGetLD2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-#endif /* _MTOT2_H_ */
-
-
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c
deleted file mode 100644
index b75f927..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c
+++ /dev/null
@@ -1,1118 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd2.c
- *
- * Technology SPD supporting functions for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
- *
- **/
-/*****************************************************************************
-*
-* Copyright (C) 2012 Advanced Micro Devices, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of Advanced Micro Devices, Inc. nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-* ***************************************************************************
-*
-*/
-
-/*
- *----------------------------------------------------------------------------
- * MODULES USED
- *
- *----------------------------------------------------------------------------
- */
-
-
-
-#include "AGESA.h"
-#include "AdvancedApi.h"
-#include "amdlib.h"
-#include "Ids.h"
-#include "mport.h"
-#include "mm.h"
-#include "mn.h"
-#include "mt.h"
-#include "mu.h"
-#include "mt2.h"
-#include "mtspd2.h"
-#include "mftds.h"
-#include "GeneralServices.h"
-#include "Filecode.h"
-CODE_GROUP (G1_PEICC)
-RDATA_GROUP (G2_PEI)
-
-#define FILECODE PROC_MEM_TECH_DDR2_MTSPD2_FILECODE
-
-/*----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS AND STRUCTURES
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * PROTOTYPES OF LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-UINT8
-STATIC
-MemTSPDGetTCL2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- );
-
-BOOLEAN
-STATIC
-MemTSysCapability2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT16 j
- );
-
-BOOLEAN
-STATIC
-MemTDimmSupports2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT8 j,
- IN UINT8 i
- );
-
-UINT8
-STATIC
-MemTGetTk2 (
- IN UINT8 k
- );
-
-UINT8
-STATIC
-MemTGetBankAddr2 (
- IN UINT8 k
- );
-
-/*----------------------------------------------------------------------------
- * EXPORTED FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-
-extern BUILD_OPT_CFG UserOptions;
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the DRAM mode
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that the DRAM mode is set to DDR2
- */
-
-BOOLEAN
-MemTSetDramMode2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- TechPtr->NBPtr->SetBitField (TechPtr->NBPtr, BFLegacyBiosMode, 0);
- return TRUE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function determines if DIMMs are present. It checks checksum and interrogates the SPDs
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTDIMMPresence2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- MEM_PARAMETER_STRUCT *RefPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 Checksum;
- UINT16 Value16;
- UINT8 Dct;
- UINT8 Channel;
- UINT8 i;
- UINT8 ByteNum;
- UINT8 Devwidth;
- UINT8 Value8;
- UINT8 MaxDimms;
- UINT8 DimmSlots;
- UINT16 DimmMask;
- BOOLEAN SPDCtrl;
-
- NBPtr = TechPtr->NBPtr;
- RefPtr = NBPtr->RefPtr;
- MCTPtr = NBPtr->MCTPtr;
-
- SPDCtrl = UserOptions.CfgIgnoreSpdChecksum;
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- ChannelPtr->DimmQrPresent = 0;
-
- // Get the maximum number of DIMMs
- DimmSlots = GetMaxDimmsPerChannel (RefPtr->PlatformMemoryConfiguration,
- MCTPtr->SocketId,
- NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
- );
- MaxDimms = MAX_DIMMS_PER_CHANNEL;
- for (i = 0; i < MaxDimms; i++) {
- // Bitmask representing dimm #i.
- DimmMask = (UINT16)1 << i;
-
- if ((ChannelPtr->DimmQrPresent & DimmMask) || (i < DimmSlots)) {
- if (MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i)) {
- MCTPtr->DimmPresent |= DimmMask;
-
- // Start by computing checksum for this SPD
- Checksum = 0;
- for (ByteNum = 0; ByteNum < SPD_CHECKSUM; ByteNum++) {
- Checksum = Checksum + (UINT16) SpdBufferPtr[ByteNum];
- }
- // Check for valid checksum value
- AGESA_TESTPOINT (TpProcMemSPDChecking, &(NBPtr->MemPtr->StdHeader));
-
- if (SpdBufferPtr[SPD_TYPE] == JED_DDR2_SDRAM) {
- ChannelPtr->ChDimmValid |= DimmMask;
- MCTPtr->DimmValid |= DimmMask;
- } else {
- // Current socket is set up to only support DDR2 dimms.
- IDS_ERROR_TRAP;
- }
- if ((SpdBufferPtr[SPD_CHECKSUM] != (UINT8)Checksum) && !SPDCtrl) {
- //
- // if NV_SPDCHK_RESTRT is set to 0,
- // cannot ignore faulty SPD checksum
- //
- // Indicate checksum error
- ChannelPtr->DimmSpdCse |= DimmMask;
- PutEventLog (AGESA_ERROR, MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- // Check module type information.
- if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_REG_ADC_MSK) {
- ChannelPtr->RegDimmPresent |= DimmMask;
- MCTPtr->RegDimmPresent |= DimmMask;
- }
-
- if (SpdBufferPtr[SPD_DIMM_TYPE] & JED_SODIMM) {
- ChannelPtr->SODimmPresent |= DimmMask;
- }
-
- // Check error correction type
- if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ECC) {
- MCTPtr->DimmEccPresent |= DimmMask; // Dimm has ECC
- }
- if (SpdBufferPtr[SPD_EDC_TYPE] & JED_ADRC_PAR) {
- MCTPtr->DimmParPresent |= DimmMask; // Dimm has parity
- }
-
- // Get the Dimm width data
- Devwidth = SpdBufferPtr[SPD_DEV_WIDTH] & 0xFE;
- if (Devwidth == 4) {
- ChannelPtr->Dimmx4Present |= DimmMask; // Dimm has parity
- } else if (Devwidth == 8) {
- ChannelPtr->Dimmx8Present |= DimmMask; // Dimm has parity
- } else if (Devwidth == 16) {
- ChannelPtr->Dimmx16Present |= DimmMask; // Dimm has parity
- }
-
- // Determine the page size.
- // page_size = 2^COLBITS * Devwidth/8
- //
- Value16 = (((UINT16)1 << SpdBufferPtr[SPD_COL_SZ]) * Devwidth) / 8;
- if (!(Value16 >> 11)) {
- DCTPtr->Timings.DIMM1KPage |= DimmMask;
- }
-
- // Check for 'analysis probe installed'
- if (SpdBufferPtr[SPD_ATTRIB] & JED_PROBE_MSK) {
- MCTPtr->Status[SbDiagClks] = TRUE;
- }
-
- // Determine the geometry of the DIMM module
- if (SpdBufferPtr[SPD_DM_BANKS] & SP_DPL_BIT) {
- ChannelPtr->DimmPlPresent |= DimmMask; // Dimm is planar
- }
-
- // specify the number of ranks
- Value8 = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
- if (Value8 > 2) {
- if (ChannelPtr->DimmQrPresent == 0) {
- // if any DIMMs are QR,
- // we have to make two passes through DIMMs
- //
- MaxDimms = MaxDimms << 1;
- }
-
- if (i < DimmSlots) {
- ChannelPtr->DimmQrPresent |= DimmMask;
- ChannelPtr->DimmQrPresent |= (DimmMask << 2);
- }
- Value8 = 2;
- } else if (Value8 == 2) {
- ChannelPtr->DimmDrPresent |= DimmMask; // Dual rank dimms
- }
-
- // Calculate bus loading per Channel
- if (Devwidth == 16) {
- Devwidth = 4;
- } else if (Devwidth == 4) {
- Devwidth = 16;
- }
- // double Addr bus load value for dual rank DIMMs
- if (Value8 == 2) {
- Devwidth = Devwidth << 1;
- }
-
- ChannelPtr->Ranks = ChannelPtr->Ranks + Value8;
- ChannelPtr->Loads = ChannelPtr->Loads + Devwidth;
- ChannelPtr->Dimms++;
-
- // Now examine the dimm packaging dates
- Value8 = SpdBufferPtr[SPD_MAN_DATE_YR];
- if (Value8 < M_YEAR_06) {
- ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006
- ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006
- } else if (Value8 == M_YEAR_06) {
- ChannelPtr->DimmYr06 |= DimmMask; // Built before end of 2006
- if (SpdBufferPtr[SPD_MAN_DATE_WK] <= M_WEEK_24) {
- ChannelPtr->DimmWk2406 |= DimmMask; // Built before end of week 24,2006
- }
- }
- } // if DIMM present
- } // Quadrank
- } // Dimm loop
-
- if (Channel == 0) {
- DCTPtr->Timings.DctDimmValid = ChannelPtr->ChDimmValid;
- DCTPtr->Timings.DimmSpdCse = ChannelPtr->DimmSpdCse;
- DCTPtr->Timings.DimmQrPresent = ChannelPtr->DimmQrPresent;
- DCTPtr->Timings.DimmDrPresent = ChannelPtr->DimmDrPresent;
- DCTPtr->Timings.Dimmx4Present = ChannelPtr->Dimmx4Present;
- DCTPtr->Timings.Dimmx8Present = ChannelPtr->Dimmx8Present;
- DCTPtr->Timings.Dimmx16Present = ChannelPtr->Dimmx16Present;
- }
- if ((Channel != 1) || (Dct != 1)) {
- MCTPtr->DimmPresent <<= 8;
- MCTPtr->DimmValid <<= 8;
- MCTPtr->RegDimmPresent <<= 8;
- MCTPtr->DimmEccPresent <<= 8;
- MCTPtr->DimmParPresent <<= 8;
- }
- } // Channel loop
- } // DCT loop
-
-
- // If we have DIMMs, some further general characteristics checking
- if (MCTPtr->DimmValid) {
- // If there are registered dimms, all the dimms must be registered
- if (MCTPtr->RegDimmPresent == MCTPtr->DimmValid) {
- // All dimms registered
- MCTPtr->Status[SbRegistered] = TRUE;
- } else if (MCTPtr->RegDimmPresent) {
- // We have an illegal DIMM mismatch
- PutEventLog (AGESA_FATAL, MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_FATAL, MCTPtr);
- }
-
- // check the ECC capability of the DIMMs
- if (MCTPtr->DimmEccPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbEccDimms] = TRUE; // All dimms ECC capable
- }
-
- // check the parity capability of the DIMMs
- if (MCTPtr->DimmParPresent == MCTPtr->DimmValid) {
- MCTPtr->Status[SbParDimms] = TRUE; // All dimms parity capable
- }
- } else {
- }
-
- NBPtr->SwitchDCT (NBPtr, 0);
- NBPtr->SwitchChannel (NBPtr, 0);
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function finds the best T and CL primary timing parameter pair, per Mfg.,for the given
- * set of DIMMs, and store into DIE_STRUCT(.Speed and .Casl).
- * See "Global relationship between index values and item values" for definition of
- * CAS latency index (j) and Frequency index (k).
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDGetTargetSpeed2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT16 SpeedCvt[] = {
- DDR400_FREQUENCY,
- DDR533_FREQUENCY,
- DDR667_FREQUENCY,
- DDR800_FREQUENCY,
- DDR1066_FREQUENCY
- };
- INT8 i;
- INT8 j;
- INT8 k;
- INT8 Dct;
- INT8 Channel;
- UINT8 T1min;
- UINT8 CL1min;
- BOOLEAN IsSupported;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- CH_DEF_STRUCT *ChannelPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = TechPtr->NBPtr->MCTPtr;
-
- CL1min = 0xFF;
- T1min = 0xFF;
-
- // For DDR2, run SyncTargetSpeed first to get frequency limit into DCTPtr->Timings.Speed
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- NBPtr->DCTPtr->Timings.TargetSpeed = 16; // initialized with big number
- }
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Find target frequency and Tcl
- for (k = K_MAX; k >= K_MIN; k--) {
- for (j = J_MIN; j <= J_MAX; j++) {
- if (MemTSysCapability2 (TechPtr, k, j)) {
- IsSupported = TRUE;
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
- NBPtr->SwitchChannel (NBPtr, Channel);
- ChannelPtr = NBPtr->ChannelPtr;
- for (i = 0; i < MAX_DIMMS_PER_CHANNEL; i++) {
- if (ChannelPtr->ChDimmValid & ((UINT8)1 << i)) {
- if (!MemTDimmSupports2 (TechPtr, k, j, i)) {
- IsSupported = FALSE;
- Dct = NBPtr->DctCount;
- Channel = NBPtr->ChannelCount;
- break;
- }
- }
- }
- }
- }
-
- if (IsSupported) {
- T1min = k;
- CL1min = j;
- // Kill the loops...
- k = K_MIN - 1;
- j = J_MAX + 1;
- }
- }
- }
- }
-
- if (T1min == 0xFF) {
- // Failsafe values, running in minimum mode
- PutEventLog (AGESA_FATAL, MEM_ERROR_MISMATCH_DIMM_CLOCKS, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- PutEventLog (AGESA_FATAL, MEM_ERROR_MINIMUM_MODE, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
-
- T1min = T_DEF;
- CL1min = CL_DEF;
- }
-
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- DCTPtr->Timings.TargetSpeed = SpeedCvt[T1min - 1];
- }
-
- // Ensure the target speed can be applied to all channels of the current node
- NBPtr->SyncTargetSpeed (NBPtr);
-
- // Set the start-up frequency
- for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
- NBPtr->SwitchDCT (NBPtr, Dct);
- DCTPtr = NBPtr->DCTPtr;
- DCTPtr->Timings.Speed = DCTPtr->Timings.TargetSpeed;
- DCTPtr->Timings.CasL = CL1min + 2; // Convert to clocks
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function check the symmetry of DIMM pairs (DIMM on Channel A matching with
- * DIMM on Channel B), the overall DIMM population, and determine the width mode:
- * 64-bit, 64-bit muxed, 128-bit.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDCalcWidth2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferAPtr;
- UINT8 *SpdBufferBPtr;
- MEM_NB_BLOCK *NBPtr;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- UINT8 i;
- UINT16 DimmMask;
- UINT8 UngangMode;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- UngangMode = UserOptions.CfgMemoryModeUnganged;
- IDS_OPTION_HOOK (IDS_GANGING_MODE, &UngangMode, &(NBPtr->MemPtr->StdHeader));
-
- // Check symmetry of channel A and channel B dimms for 128-bit mode
- // capability.
- //
- AGESA_TESTPOINT (TpProcMemModeChecking, &(NBPtr->MemPtr->StdHeader));
- i = 0;
- if (MCTPtr->DctData[0].Timings.DctDimmValid == MCTPtr->DctData[1].Timings.DctDimmValid) {
- for (; i < MAX_DIMMS_PER_CHANNEL; i++) {
- DimmMask = (UINT16)1 << i;
- if (DCTPtr->Timings.DctDimmValid & DimmMask) {
- NBPtr->SwitchDCT (NBPtr, 0);
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferAPtr, i);
- NBPtr->SwitchDCT (NBPtr, 1);
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferBPtr, i);
-
- if ((SpdBufferAPtr[SPD_ROW_SZ]&0x1F) != (SpdBufferBPtr[SPD_ROW_SZ]&0x1F)) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_COL_SZ]&0x1F) != (SpdBufferBPtr[SPD_COL_SZ]&0x1F)) {
- break;
- }
-
- if (SpdBufferAPtr[SPD_BANK_SZ] != SpdBufferBPtr[SPD_BANK_SZ]) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_DEV_WIDTH]&0x7F) != (SpdBufferBPtr[SPD_DEV_WIDTH]&0x7F)) {
- break;
- }
-
- if ((SpdBufferAPtr[SPD_DM_BANKS]&0x07) != (SpdBufferBPtr[SPD_DM_BANKS]&0x07)) {
- break;
- }
- }
- }
- }
- if (i < MAX_DIMMS_PER_CHANNEL) {
- PutEventLog (AGESA_ALERT, MEM_ALERT_ORG_MISMATCH_DIMM, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ALERT, MCTPtr);
- } else if (!UngangMode) {
- NBPtr->Ganged = TRUE;
- MCTPtr->GangedMode = TRUE;
- MCTPtr->Status[Sb128bitmode] = TRUE;
- NBPtr->SetBitField (NBPtr, BFDctGangEn, 1);
- }
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Initialize DCT Timing registers as per DIMM SPD.
- * For primary timing (T, CL) use best case T value.
- * For secondary timing params., use most aggressive settings
- * of slowest DIMM.
- *
- * Note:
- * There are three components to determining "maximum frequency": SPD component,
- * Bus load component, and "Preset" max frequency component.
- * The SPD component is a function of the min cycle time specified by each DIMM,
- * and the interaction of cycle times from all DIMMs in conjunction with CAS
- * latency. The SPD component only applies when user timing mode is 'Auto'.
- *
- * The Bus load component is a limiting factor determined by electrical
- * characteristics on the bus as a result of varying number of device loads. The
- * Bus load component is specific to each platform but may also be a function of
- * other factors. The bus load component only applies when user timing mode is
- * ' Auto'.
- *
- * The Preset component is subdivided into three items and is the minimum of
- * the set: Silicon revision, user limit setting when user timing mode is 'Auto' and
- * memclock mode is 'Limit', OEM build specification of the maximum frequency.
- * The Preset component only applies when user timing mode is 'Auto'.
-
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTAutoCycTiming2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- CONST UINT8 SpdIndexes[] = {
- SPD_TRCD,
- SPD_TRP,
- SPD_TRTP,
- SPD_TRAS,
- SPD_TRC,
- SPD_TWR,
- SPD_TRRD,
- SPD_TWTR
- };
- CONST UINT8 Multiples[] = {10, 10, 10, 40, 40, 10, 10, 10};
-
- CONST UINT8 Tab1KTfawTK[] = {8, 10, 13, 14, 0, 20};
- CONST UINT8 Tab2KTfawTK[] = {10, 14, 17, 18, 0, 24};
- CONST UINT8 TabDefTrcK[] = {0x41, 0x3C, 0x3C, 0x3A, 0, 0x3A};
-
- UINT8 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)];
- UINT8 MiniMaxTrfc[4];
-
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
- UINT16 DimmMask;
- UINT16 Value16;
- UINT16 Tk40;
- UINT8 i;
- UINT8 j;
- UINT8 Value8;
- UINT8 Temp8;
- UINT8 *StatTmgPtr;
- UINT16 *StatDimmTmgPtr;
- BOOLEAN Is1066;
- UINT8 *SpdBufferPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- // initialize mini-max arrays
- for (j = 0; j < GET_SIZE_OF (MiniMaxTmg); j++) {
- MiniMaxTmg[j] = 0;
- }
- for (j = 0; j < GET_SIZE_OF (MiniMaxTrfc); j++) {
- MiniMaxTrfc[j] = 0;
- }
-
- // ======================================================================
- // Get primary timing (CAS Latency and Cycle Time)
- // ======================================================================
- // Get OEM specific load variant max
- //
-
- //======================================================================
- // Gather all DIMM mini-max values for cycle timing data
- //======================================================================
- //
- DimmMask = 1;
- for (i = 0; i < (MAX_CS_PER_CHANNEL / 2); i++) {
- if (DCTPtr->Timings.DctDimmValid & DimmMask) {
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value8 = SpdBufferPtr[SpdIndexes[j]];
- if (SpdIndexes[j] == SPD_TRC) {
- if (Value8 == 0 || Value8 == 0xFF) {
- PutEventLog (AGESA_WARNING, MEM_WARNING_NO_SPDTRC_FOUND, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, i, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, MCTPtr);
- Value8 = TabDefTrcK[(DCTPtr->Timings.Speed / 66) - 3];
- }
- }
- if (MiniMaxTmg[j] < Value8) {
- MiniMaxTmg[j] = Value8;
- }
- }
-
- // get Trfc0 - Trfc3 values
- Value8 = SpdBufferPtr[SPD_BANK_SZ];
- Temp8 = (Value8 << 3) | (Value8 >> 5);
- Value8 = SpdBufferPtr[SPD_DEV_WIDTH];
- ASSERT (LibAmdBitScanReverse ((UINT32)Value8) <= 4);
- Temp8 >>= 4 - LibAmdBitScanReverse ((UINT32)Value8);
- Value8 = LibAmdBitScanReverse ((UINT32)Temp8);
- if (MiniMaxTrfc[i] < Value8) {
- MiniMaxTrfc[i] = Value8;
- }
- }
- DimmMask <<= 1;
- }
-
- // ======================================================================
- // Convert DRAM CycleTiming values and store into DCT structure
- // ======================================================================
- //
- Tk40 = 40000 / DCTPtr->Timings.Speed;
- if (DCTPtr->Timings.Speed == DDR1066_FREQUENCY) {
- Is1066 = TRUE;
- } else {
- Is1066 = FALSE;
- }
- // Notes:
- // 1. All secondary time values given in SPDs are in binary with UINTs of ns.
- // 2. Some time values are scaled by four, in order to have least count of 0.25 ns
- // (more accuracy). JEDEC SPD spec. shows which ones are x1 and x4.
- // 3. Internally to this SW, cycle time, Tk, is scaled by 10 to affect a
- // least count of 0.1 ns (more accuracy).
- // 4. SPD values not scaled are multiplied by 10 and then divided by 10T to find
- // equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
- // 5. SPD values that are prescaled by 4 are multiplied by 10 and then divided by 40T to find
- // equivalent minimum number of bus clocks (a remainder causes round-up of clocks).
- //
- StatDimmTmgPtr = &DCTPtr->Timings.DIMMTrcd;
- StatTmgPtr = &DCTPtr->Timings.Trcd;
- for (j = 0; j < GET_SIZE_OF (SpdIndexes); j++) {
- Value16 = (UINT16)MiniMaxTmg[j] * Multiples[j];
- StatDimmTmgPtr[j] = Value16;
-
- MiniMaxTmg[j] = (UINT8) ((Value16 + Tk40 - 1) / Tk40);
- if (SpdIndexes[j] == SPD_TRTP) {
- MiniMaxTmg[j] = (DCTPtr->Timings.Speed <= DDR533_FREQUENCY) ? 2 : 3; // based on BL of 32 bytes
- }
-
- StatTmgPtr[j] = MiniMaxTmg[j];
- }
- DCTPtr->Timings.Trfc0 = MiniMaxTrfc[0];
- DCTPtr->Timings.Trfc1 = MiniMaxTrfc[1];
- DCTPtr->Timings.Trfc2 = MiniMaxTrfc[2];
- DCTPtr->Timings.Trfc3 = MiniMaxTrfc[3];
-
- DCTPtr->Timings.CasL = MemTSPDGetTCL2 (TechPtr);
-
- if (DCTPtr->Timings.DIMM1KPage) {
- DCTPtr->Timings.Tfaw = Tab1KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
- } else {
- DCTPtr->Timings.Tfaw = Tab2KTfawTK[(DCTPtr->Timings.Speed / 66) - 3];
- }
- if (Is1066) {
- DCTPtr->Timings.Tfaw >>= 1;
- }
-
- //======================================================================
- // Program DRAM Timing values
- //======================================================================
- //
- NBPtr->ProgramCycTimings (NBPtr);
-
- MemFInitTableDrive (NBPtr, MTAfterAutoCycTiming);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function sets the bank addressing, program Mask values and build a chip-select population map.
- * This routine programs PCI 0:24N:2x80 config register.
- * This routine programs PCI 0:24N:2x60,64,68,6C config registers (CS Mask 0-3)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return TRUE - indicates that a FATAL error has not occurred
- * @return FALSE - indicates that a FATAL error has occurred
- */
-
-BOOLEAN
-MemTSPDSetBanks2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- UINT8 *SpdBufferPtr;
- UINT8 i;
- UINT8 ChipSel;
- UINT8 DimmID;
- UINT8 Value8;
- UINT8 Rows;
- UINT8 Cols;
- UINT8 Ranks;
- UINT8 Banks;
- UINT32 BankAddrReg;
- UINT32 CsMask;
- UINT16 CSSpdCSE;
- UINT16 CSExclude;
- UINT16 DimmQRDR;
- DIE_STRUCT *MCTPtr;
- DCT_STRUCT *DCTPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
- MCTPtr = NBPtr->MCTPtr;
- DCTPtr = NBPtr->DCTPtr;
-
- BankAddrReg = 0;
- CSSpdCSE = 0;
- CSExclude = 0;
- for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) {
- DimmID = ChipSel >> 1;
-
- DimmQRDR = (DCTPtr->Timings.DimmQrPresent) | (DCTPtr->Timings.DimmDrPresent);
- if (DCTPtr->Timings.DimmSpdCse & (UINT16) 1 << DimmID) {
- CSSpdCSE |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3 : 1) << ChipSel;
- }
- if ((DCTPtr->Timings.DimmExclude & ((UINT16) 1 << DimmID)) != 0) {
- CSExclude |= (UINT16) ((DimmQRDR & (UINT16) 1 << DimmID) ? 3: 1) << ChipSel;
- }
-
- if (DCTPtr->Timings.DctDimmValid & ((UINT16)1 << DimmID)) {
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, DimmID);
-
- // Get the basic data
- Rows = SpdBufferPtr[SPD_ROW_SZ] & 0x1F;
- Cols = SpdBufferPtr[SPD_COL_SZ] & 0x1F;
- Banks = SpdBufferPtr[SPD_L_BANKS];
- Ranks = (SpdBufferPtr[SPD_DM_BANKS] & 0x07) + 1;
-
- // Configure the bank encoding
- Value8 = (Cols - 9) << 3;
- Value8 |= (Banks == 8) ? 4 : 0;
- Value8 |= (Rows - 13);
-
- for (i = 0; i < 12; i++) {
- if (Value8 == MemTGetBankAddr2 (i)) {
- break;
- }
- }
-
- if (i < 12) {
- BankAddrReg |= ((UINT32)i << (ChipSel << 1));
-
- // Mask value=(2pow(rows+cols+banks+3)-1)>>8,
- // or 2pow(rows+cols+banks-5)-1
- //
- Value8 = Rows + Cols;
- Value8 -= (Banks == 8) ? 2:3;
- if (MCTPtr->Status[Sb128bitmode]) {
- Value8++;
- }
- CsMask = ((UINT32)1 << Value8) - 1;
- DCTPtr->Timings.CsPresent |= (UINT16)1 << ChipSel;
-
- if (Ranks >= 2) {
- DCTPtr->Timings.CsPresent |= (UINT16)1 << (ChipSel + 1);
- }
-
- // Update the DRAM CS Mask for this chipselect
- NBPtr->SetBitField (NBPtr, BFCSMask0Reg + (ChipSel >> 1), (CsMask & NBPtr->CsRegMsk));
- }
- }
- }
- // For ranks that need to be excluded, the loading of this rank should be considered
- // in timing, so need to set CsPresent before setting CsTestFail
- if ((CSSpdCSE != 0) || (CSExclude != 0)) {
- if (!NBPtr->MemPtr->ErrorHandling (MCTPtr, NBPtr->Dct, (CSSpdCSE | CSExclude), &NBPtr->MemPtr->StdHeader)) {
- ASSERT (FALSE);
- }
- }
-
- // If there are no chip selects, we have an error situation.
- if (DCTPtr->Timings.CsPresent == 0) {
- PutEventLog (AGESA_ERROR, MEM_ERROR_NO_CHIPSELECT, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_ERROR, MCTPtr);
- }
-
- NBPtr->SetBitField (NBPtr, BFDramBankAddrReg, BankAddrReg);
-
- return (BOOLEAN) (MCTPtr->ErrCode < AGESA_FATAL);
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the low bit that will be swapped to enable CS interleaving
- *
- * @param[in] BankEnc - AddrMap Bank encoding from F2x80
- * @param[in] *LowBit - pointer to low bit
- * @param[in] *HiBit - pointer hight bit
- *
- */
-
-VOID
-MemTGetCSIntLvAddr2 (
- IN UINT8 BankEnc,
- OUT UINT8 *LowBit,
- OUT UINT8 *HiBit
- )
-{
- CONST UINT8 ArrCodesLo[] = {6, 7, 7, 8, 8, 8, 8, 8, 9, 9, 8, 9};
- CONST UINT8 ArrCodesHi[] = {19, 20, 21, 21, 21, 22, 22, 23, 23, 24, 24, 25};
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesLo));
- ASSERT (BankEnc < GET_SIZE_OF (ArrCodesHi));
- // return ArrCodes[BankEnc];
- *LowBit = ArrCodesLo[BankEnc];
- *HiBit = ArrCodesHi[BankEnc];
-}
-
-/*----------------------------------------------------------------------------
- * LOCAL FUNCTIONS
- *
- *----------------------------------------------------------------------------
- */
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the CAS latency of the current frequency.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- *
- * @return CAS Latency
- */
-UINT8
-STATIC
-MemTSPDGetTCL2 (
- IN OUT MEM_TECH_BLOCK *TechPtr
- )
-{
- return TechPtr->NBPtr->DCTPtr->Timings.CasL;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Get max frequency from OEM platform definition, from
- * any user override (limiting) of max frequency, and
- * from any Si Revision Specific information. Return
- * the least of these three in DIE_STRUCT.PresetmaxFreq.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] k - Frequency index
- * @param[in] j - CAS Latency index
- *
- * @return TRUE - (k << 8) | j
- * @return FALSE - 0
- */
-
-BOOLEAN
-STATIC
-MemTSysCapability2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT16 j
- )
-{
- if ((k > TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed) || (j > J_MAX)) {
- return FALSE;
- }
-
- return TRUE; //(k << 8) | j;
-}
-
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * Determine whether dimm(b,i) supports CL(j) and F(k)
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in] k - Frequency index
- * @param[in] j - CAS Latency index
- * @param[in] i - DIMM number
- *
- * @return TRUE - DIMM supports
- * @return FALSE - DIMM does not support
- */
-
-BOOLEAN
-STATIC
-MemTDimmSupports2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN UINT8 k,
- IN UINT8 j,
- IN UINT8 i
- )
-{
- CONST UINT8 SpdBytesForCL[3] = { 9, 23, 25}; // SPD bytes for CL X, CL X-.5, and CL X-1
- UINT8 CLj;
- UINT8 CLi;
- UINT8 T1;
- UINT8 T2;
- UINT8 Tk;
- UINT8 *SpdBufferPtr;
- MEM_NB_BLOCK *NBPtr;
-
- NBPtr = TechPtr->NBPtr;
-
- MemTGetDimmSpdBuffer2 (TechPtr, &SpdBufferPtr, i);
- CLj = (UINT8) 1 << (j + 2);
- CLi = SpdBufferPtr[SPD_CAS_LAT];
-
- if (CLj & CLi) {
- // If this dimm supports the desired CAS latency...
- // Determine the SPD location of the dimm speed UINT8 appropriate
- // to the CAS latency indicated by Table_CL2_j.
- //
- T1 = LibAmdBitScanReverse ((UINT32)CLj);
- T2 = LibAmdBitScanReverse ((UINT32)CLi);
- ASSERT ((T2 - T1) < 3);
- CLi = SpdBufferPtr[SpdBytesForCL[(T2 - T1)]];
- Tk = MemTGetTk2 (k);
- if (CLi == 0) {
- PutEventLog (AGESA_FATAL, MEM_ERROR_NO_CYC_TIME, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
- SetMemError (AGESA_WARNING, NBPtr->MCTPtr);
- } else if (Tk >= CLi) {
- return TRUE;
- }
- }
- return FALSE;
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the cycle time
- *
- * @param[in] k - CAS Latency index
- *
- * @return Tk as specified by JEDEC SPD byte 9.
- */
-
-UINT8
-STATIC
-MemTGetTk2 (
- IN UINT8 k
- )
-{
- CONST UINT8 TableTK[] = {0x00, 0x50, 0x3D, 0x30, 0x25, 0x18};
- ASSERT (k < GET_SIZE_OF (TableTK));
- return TableTK[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns the encoded value of bank address.
- *
- * @param[in] k value
- *
- * @return RRRBCC, where CC is the number of Columns minus 9,
- * RRR is the number of Rows minus 12, and B is the number of banks
- * minus 3.
- */
-
-UINT8
-STATIC
-MemTGetBankAddr2 (
- IN UINT8 k
- )
-{
- CONST UINT8 TabBankAddr[] = {
- 0x00, 0x08, 0x09, 0x10, 0x0C, 0x0D,
- 0x11, 0x0E, 0x15, 0x16, 0x0F, 0x17
- };
- ASSERT (k < GET_SIZE_OF (TabBankAddr));
- return TabBankAddr[k];
-}
-
-/* -----------------------------------------------------------------------------*/
-/**
- *
- * This function returns a pointer to the SPD Buffer of a specific dimm on
- * the current channel.
- *
- * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
- * @param[in,out] **SpdBuffer - Pointer to a pointer to a UINT8 Buffer
- * @param[in] Dimm - Dimm number
- *
- *
- * @return BOOLEAN - Value of DimmPresent
- * TRUE = Dimm is present, pointer is valid
- * FALSE = Dimm is not present, pointer has not been modified.
- */
-
-BOOLEAN
-MemTGetDimmSpdBuffer2 (
- IN OUT MEM_TECH_BLOCK *TechPtr,
- IN OUT UINT8 **SpdBuffer,
- IN UINT8 Dimm
- )
-{
- CH_DEF_STRUCT *ChannelPtr;
- SPD_DEF_STRUCT *SPDPtr;
- BOOLEAN DimmPresent;
-
- DimmPresent = FALSE;
- ChannelPtr = TechPtr->NBPtr->ChannelPtr;
- ASSERT (Dimm < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])))
- SPDPtr = ChannelPtr->DimmSpdPtr[Dimm];
-
-
- if (SPDPtr != NULL) {
- DimmPresent = SPDPtr->DimmPresent;
- if (DimmPresent) {
- *SpdBuffer = SPDPtr->Data;
- }
- }
- return DimmPresent;
-}
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h
deleted file mode 100644
index b115888..0000000
--- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * mtspd2.h
- *
- * Technology SPD support for DDR2
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: (Mem/Tech/DDR2)
- * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
- *
- **/
-/*****************************************************************************
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ***************************************************************************
- *
- */
-
-#ifndef _MTSPD2_H_
-#define _MTSPD2_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-
-/*===============================================================================
- * Jedec DDR II
- *===============================================================================
- */
-#define SPD_TYPE 2 /* SPD byte read location */
-#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
-#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
-
-#define SPD_DIMM_TYPE 20
-#define SPD_ATTRIB 21
-#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
-#define JED_REG_ADC_MSK 0x11 /* Registered Address/Control */
-#define JED_PROBE_MSK 0x40 /* Analysis Probe installed */
-#define JED_SODIMM 0x04 /* SO-DIMM */
-#define SPD_DEV_ATTRIB 22
-#define SPD_EDC_TYPE 11
-#define JED_ECC 2
-#define JED_ADRC_PAR 4
-#define SPD_ROW_SZ 3
-#define SPD_COL_SZ 4
-#define SPD_L_BANKS 17 /* number of [logical] banks on each device */
-#define SPD_DM_BANKS 5 /* number of physical banks on dimm */
-#define SP_DPL_BIT 4 /* Dram package bit */
-#define SPD_BANK_SZ 31 /* capacity of physical bank */
-#define SPD_DEV_WIDTH 13
-#define SPD_CAS_LAT 18
-#define SPD_TRP 27
-#define SPD_TRRD 28
-#define SPD_TRCD 29
-#define SPD_TRAS 30
-#define SPD_TWR 36
-#define SPD_TWTR 37
-#define SPD_TRTP 38
-#define SPD_TRC 41
-#define SPD_TRFC 42
-#define SPD_CHECKSUM 63
-#define SPD_MAN_DATE_YR 93 /* Module Manufacturing Year (BCD) */
-
-#define SPD_MAN_DATE_WK 94 /* Module Manufacturing Week (BCD) */
-
-/*-----------------------------
- * Jedec DDR II related equates
- *-----------------------------
- */
-#define M_YEAR_06 0x06 /* Manufacturing Year BCD encoding of 2006 - 06d */
-#define M_WEEK_24 0x24 /* Manufacturing Week BCD encoding of June - 24d */
-
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T */
-#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T */
-#define K_MIN 1 /* k loop constraint. 1=200 MHz */
-#define K_MAX 5 /* k loop constraint. 5=533 MHz */
-#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T */
-#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time) */
-
-
-#define BIAS_TCL_T 1
-#define BIAS_TRP_T 3 /* bias to convert bus clocks to bit field value */
-#define BIAS_TRRD_T 2
-#define BIAS_TRCD_T 3
-#define BIAS_TRAS_T 3
-#define BIAS_TRC_T 11
-#define BIAS_TRTP_T 1
-#define BIAS_TWR_T 3
-#define BIAS_TWTR_T 0
-#define BIAS_TFAW_T 7
-
-#define MIN_TRP_T 3 /* min programmable value in busclocks */
-#define MAX_TRP_T 6 /* max programmable value in busclocks */
-#define MIN_TRRD_T 2
-#define MAX_TRRD_T 5
-#define MIN_TRCD_T 3
-#define MAX_TRCD_T 6
-#define MIN_TRAS_T 5
-#define MAX_TRAS_T 18
-#define MIN_TRC_T 11
-#define MAX_TRC_T 26
-#define MIN_TRTP_T 2
-#define MAX_TRTP_T 4
-#define MIN_TWR_T 3
-#define MAX_TWR_T 6
-#define MIN_TWTR_T 1
-#define MAX_TWTR_T 3
-
-/* DDR2-1066 support */
-#define BIAS_TRCD_T_1066 5
-#define BIAS_TRAS_T_1066 15
-#define BIAS_TRRD_T_1066 4
-#define BIAS_TWR_T_1066 4
-#define BIAS_TRP_T_1066 5
-#define BIAS_TWTR_T_1066 4
-
-#define MIN_TRCD_T_1066 5
-#define MAX_TRCD_T_1066 12
-#define MIN_TRAS_T_1066 15
-#define MAX_TRAS_T_1066 30
-#define MIN_TRC_T_1066 11
-#define MAX_TRC_T_1066 42
-#define MIN_TRRD_T_1066 4
-#define MAX_TRRD_T_1066 7
-#define MIN_TWR_T_1066 5
-#define MAX_TWR_T_1066 8
-#define MIN_TRP_T_1066 5
-#define MAX_TRP_T_1066 12
-#define MIN_TWTR_T_1066 4
-#define MAX_TWTR_T_1066 7
-
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-
-
-#endif /* _MTSPD2_H_ */
-
-
