UPSTREAM: intel/soc/apollolake: Use intel/common/uart driver
BUG=none
BRANCH=none
TEST=none
Change-Id: I6652e6d451d5bb5969e14c081c51eca98ad6db9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf6dfaefc2fd2f22e55e3227d8b023bcd992cae5
Original-Change-Id: I6829eca34d983cfcc86074ef593cd92236b25ac5
Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19204
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/475717
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 7ec97bf..dc639a2 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -57,6 +57,8 @@
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_RTC
+ select SOC_INTEL_COMMON_BLOCK_SA
+ select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_SMI
select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 62fe47b..8a56890 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -145,7 +145,7 @@
/* Prepare UART for serial console. */
if (IS_ENABLED(CONFIG_SOC_UART_DEBUG))
- soc_console_uart_init();
+ pch_uart_init();
if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))
tpm_enable();
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
index c7ba4a6..b2b1bb8 100644
--- a/src/soc/intel/apollolake/include/soc/uart.h
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -18,9 +18,14 @@
#ifndef _SOC_APOLLOLAKE_UART_H_
#define _SOC_APOLLOLAKE_UART_H_
-void lpss_console_uart_init(void);
+/*
+* M and N divisor values for clock frequency configuration.
+* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
+*/
+#define CLK_M_VAL 0x025a
+#define CLK_N_VAL 0x7fff
/* Initialize the console UART including the pads for the configured UART. */
-void soc_console_uart_init(void);
+void pch_uart_init(void);
#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index 0a32b71..311e580 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -17,7 +17,7 @@
#include <console/uart.h>
#include <device/pci.h>
-#include <intelblocks/lpss.h>
+#include <intelblocks/uart.h>
#include <soc/gpio.h>
#include <soc/uart.h>
#include <soc/pci_devs.h>
@@ -31,32 +31,6 @@
return 0;
}
-void lpss_console_uart_init(void)
-{
- uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
- device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
-
- if (invalid_uart_for_console())
- return;
-
- /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
- pci_write_config32(uart, PCI_BASE_ADDRESS_0, base);
-
- /* Enable memory access and bus master */
- pci_write_config32(uart, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- /* Take UART out of reset */
- lpss_reset_release(base);
-
- /*
- * Set M and N divisor inputs and enable clock. These values
- * get us a 1.836 MHz clock (ideally we want 1.843 MHz)
- */
- lpss_clk_update(base, 0x025a, 0x7fff);
-
-}
-
uintptr_t uart_platform_base(int idx)
{
return CONFIG_CONSOLE_UART_BASE_ADDRESS;
@@ -69,8 +43,11 @@
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
};
-void soc_console_uart_init(void)
+void pch_uart_init(void)
{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+ device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
/* Get a 0-based pad index. See invalid_uart_for_console() above. */
const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
@@ -80,5 +57,7 @@
/* Configure the 2 pads per UART. */
gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
- lpss_console_uart_init();
+ /* Program UART2 BAR0, command, reset and clock register */
+ uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL);
+
}
