| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2015 Intel Corp. |
| * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef _SOC_APOLLOLAKE_UART_H_ |
| #define _SOC_APOLLOLAKE_UART_H_ |
| |
| /* |
| * M and N divisor values for clock frequency configuration. |
| * These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) |
| */ |
| #define CLK_M_VAL 0x025a |
| #define CLK_N_VAL 0x7fff |
| |
| /* Initialize the console UART including the pads for the configured UART. */ |
| void pch_uart_init(void); |
| |
| #endif /* _SOC_APOLLOLAKE_UART_H_ */ |
