rockchip: move vop driver from rk3288 to rockchip common
The rk3288 and rk3399 can use a common driver even that
there are some different registers.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=boot from veyron_jerry and check display
Change-Id: I063e3eebc836debc01c450d8ab9f1524c9a47c56
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/341633
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
diff --git a/src/soc/rockchip/rk3288/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h
similarity index 93%
rename from src/soc/rockchip/rk3288/include/soc/vop.h
rename to src/soc/rockchip/common/include/soc/vop.h
index b3cd9ff..f5ce431 100644
--- a/src/soc/rockchip/rk3288/include/soc/vop.h
+++ b/src/soc/rockchip/common/include/soc/vop.h
@@ -13,12 +13,12 @@
* GNU General Public License for more details.
*/
-#ifndef _RK3288_LCD_H_
-#define _RK3288_LCD_H_
+#ifndef _ROCKCHIP_LCD_H_
+#define _ROCKCHIP_LCD_H_
#include <stdint.h>
#include <edid.h>
-struct rk3288_vop_regs {
+struct rockchip_vop_regs {
u32 reg_cfg_done;
u32 version_info;
u32 sys_ctrl;
@@ -27,11 +27,22 @@
u32 dsp_ctrl1;
u32 dsp_bg;
u32 mcu_ctrl;
- u32 intr_ctrl0;
- u32 intr_ctrl1;
- u32 intr_reserved0;
- u32 intr_reserved1;
-
+ union {
+ u32 intr_ctrl0; /* RK3288 */
+ u32 wb_ctrl0; /* RK3399 */
+ };
+ union {
+ u32 intr_ctrl1; /* RK3288 */
+ u32 wb_ctrl1; /* RK3399 */
+ };
+ union {
+ u32 intr_reserved0; /* RK3288 */
+ u32 wb_yrgb_mst; /* RK3399 */
+ };
+ union {
+ u32 intr_reserved1; /* RK3288 */
+ u32 wb_cbr_mst; /* RK3399 */
+ };
u32 win0_ctrl0;
u32 win0_ctrl1;
u32 win0_color_key;
@@ -47,8 +58,10 @@
u32 win0_src_alpha_ctrl;
u32 win0_dst_alpha_ctrl;
u32 win0_fading_ctrl;
- u32 win0_reserved0;
-
+ union {
+ u32 win0_reserved0; /* RK3288 */
+ u32 win0_ctrl2; /* RK3399 */
+ };
u32 win1_ctrl0;
u32 win1_ctrl1;
u32 win1_color_key;
@@ -64,7 +77,10 @@
u32 win1_src_alpha_ctrl;
u32 win1_dst_alpha_ctrl;
u32 win1_fading_ctrl;
- u32 win1_reservd0;
+ union {
+ u32 win1_reservd0; /* RK3288 */
+ u32 win1_ctrl2; /* RK3399 */
+ };
u32 reserved2[48];
u32 post_dsp_hact_info;
u32 post_dsp_vact_info;
@@ -79,7 +95,7 @@
u32 dsp_vs_st_end_f1;
u32 dsp_vact_st_end_f1;
};
-check_member(rk3288_vop_regs, dsp_vact_st_end_f1, 0x19c);
+check_member(rockchip_vop_regs, dsp_vact_st_end_f1, 0x19c);
enum rockchip_fb_data_format_t {
ARGB8888 = 0,
@@ -97,9 +113,9 @@
};
enum vop_modes {
- /* EDP == 0 is used for early RK3288 products and is the most likely
- * use case, so keep it as the default. Other desired modes should
- * be set explicitly in the board's devicetree.cb.
+ /* EDP == 0 is used for most RK3288 products and is the most likely
+ * use case for RK3399, so keep it as the default. Other desired
+ * modes should be set explicitly in the board's devicetree.cb.
*/
VOP_MODE_EDP = 0,
VOP_MODE_HDMI,
diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/common/vop.c
similarity index 86%
rename from src/soc/rockchip/rk3288/vop.c
rename to src/soc/rockchip/common/vop.c
index 607cf8f..668bee0 100644
--- a/src/soc/rockchip/rk3288/vop.c
+++ b/src/soc/rockchip/common/vop.c
@@ -24,11 +24,10 @@
#include <soc/edp.h>
#include <soc/vop.h>
-#include "chip.h"
-static struct rk3288_vop_regs * const vop_regs[] = {
- (struct rk3288_vop_regs *)VOP_BIG_BASE,
- (struct rk3288_vop_regs *)VOP_LIT_BASE
+static struct rockchip_vop_regs * const vop_regs[] = {
+ (struct rockchip_vop_regs *)VOP_BIG_BASE,
+ (struct rockchip_vop_regs *)VOP_LIT_BASE
};
void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid)
@@ -42,7 +41,7 @@
u32 vsync_len = edid->mode.vspw;
u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
u32 xpos = 0, ypos = 0;
- struct rk3288_vop_regs *preg = vop_regs[vop_id];
+ struct rockchip_vop_regs *preg = vop_regs[vop_id];
write32(&preg->win0_act_info,
V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1));
@@ -89,7 +88,10 @@
write32(&preg->win0_yrgb_mst, fbbase);
- write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
+ /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
+ * but it's fine to write to it
+ */
+ write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */
}
void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode)
@@ -102,7 +104,7 @@
u32 vfront_porch = edid->mode.vso;
u32 vsync_len = edid->mode.vspw;
u32 vback_porch = edid->mode.vbl - edid->mode.vso - edid->mode.vspw;
- struct rk3288_vop_regs *preg = vop_regs[vop_id];
+ struct rockchip_vop_regs *preg = vop_regs[vop_id];
switch (mode) {
@@ -117,7 +119,6 @@
M_ALL_OUT_EN, V_EDP_OUT_EN(1));
break;
}
-
clrsetbits_le32(&preg->dsp_ctrl0,
M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL,
V_DSP_OUT_MODE(15) |
@@ -146,5 +147,8 @@
V_VAEP(vsync_len + vback_porch + vactive) |
V_VASP(vsync_len + vback_porch));
- write32(&preg->reg_cfg_done, 0x01); /* enable reg config */
+ /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only,
+ * but it's fine to write to it
+ */
+ write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */
}
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index 8a9b9da..a10ccd9 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -67,7 +67,7 @@
ramstage-y += gpio.c
ramstage-y += ../common/rk808.c
ramstage-y += ../common/pwm.c
-ramstage-y += vop.c
+ramstage-y += ../common/vop.c
ramstage-y += ../common/edp.c
ramstage-y += hdmi.c
ramstage-y += display.c
