Skylake boards: Enabling HWP
This patch provides config options to enable/disable Intel SST.
BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu/lars, verified HWP driver load successfully.
CQ-DEPEND=CL:313107
Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/326650
Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index ac3a5c1..bb925ce 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -16,6 +16,9 @@
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 894f0e1..89fcff8 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -16,6 +16,9 @@
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index cf3649a..50b3e1e 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -15,6 +15,9 @@
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
# Enable DPTF
register "dptf_enable" = "1"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index d2a70c8..62a0c26 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -15,6 +15,9 @@
# EC host command range is in 0x800-0x8ff
register "gen1_dec" = "0x00fc0801"
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
# Enable DPTF
register "dptf_enable" = "1"
