purin: convert readl/writel to read32/write32
This patch changes accessor macros from readl/writel to read32/write32.
There is no functionality change.
BUG=none
BRANCH=tot
TEST=built coreboot for purin
Change-Id: Ib80c2537cbf5c52f19207dd0a8c7816be89eed6e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/268997
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@google.com>
Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Trybot-Ready: Daisuke Nojiri <dnojiri@google.com>
diff --git a/src/soc/broadcom/cygnus/gpio.c b/src/soc/broadcom/cygnus/gpio.c
index f21f6ae..d9b196a 100644
--- a/src/soc/broadcom/cygnus/gpio.c
+++ b/src/soc/broadcom/cygnus/gpio.c
@@ -208,13 +208,13 @@
static u32 cygnus_readl(struct cygnus_gpio *chip, unsigned int offset)
{
- return readl(chip->base + offset);
+ return read32(chip->base + offset);
}
static void cygnus_writel(struct cygnus_gpio *chip, unsigned int offset,
u32 val)
{
- writel(val, chip->base + offset);
+ write32(chip->base + offset, val);
}
/**
diff --git a/src/soc/broadcom/cygnus/hw_init.c b/src/soc/broadcom/cygnus/hw_init.c
index 65d6bc2..c472cc1 100644
--- a/src/soc/broadcom/cygnus/hw_init.c
+++ b/src/soc/broadcom/cygnus/hw_init.c
@@ -47,7 +47,7 @@
* Enable NS SCU access to ARM global timer, private timer, and
* components
*/
- writel(0xFFF, (void *)IHOST_SCU_SECURE_ACCESS);
+ write32((void *)IHOST_SCU_SECURE_ACCESS, 0xFFF);
}
static void smau_ns_config(void)
@@ -55,9 +55,9 @@
unsigned int val;
/* Disable SMAU NIC IDM TZ */
- val = readl((void *)SMAU_NIC_IDM_TZ_BASE);
+ val = read32((void *)SMAU_NIC_IDM_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
- writel(val, (void *)SMAU_NIC_IDM_TZ_BASE);
+ write32((void *)SMAU_NIC_IDM_TZ_BASE, val);
/*
* Disable DDR TZ base
@@ -67,9 +67,9 @@
* NOTE: In the future, multiple regions of DDR may need to be marked
* as SECURE for secure OS and other TZ usages
*/
- val = readl((void *)SMAU_DDR_TZ_BASE);
+ val = read32((void *)SMAU_DDR_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
- writel(val, (void *)SMAU_DDR_TZ_BASE);
+ write32((void *)SMAU_DDR_TZ_BASE, val);
/*
@@ -82,24 +82,24 @@
*/
/* Flash 0: ROM */
- val = readl((void *)SMAU_FLASH0_TZ_BASE);
+ val = read32((void *)SMAU_FLASH0_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
- writel(val, (void *)SMAU_FLASH0_TZ_BASE);
+ write32((void *)SMAU_FLASH0_TZ_BASE, val);
/* Flash 1: QSPI */
- val = readl((void *)SMAU_FLASH1_TZ_BASE);
+ val = read32((void *)SMAU_FLASH1_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
- writel(val, (void *)SMAU_FLASH1_TZ_BASE);
+ write32((void *)SMAU_FLASH1_TZ_BASE, val);
/* Flash 2: NAND */
- val = readl((void *)SMAU_FLASH2_TZ_BASE);
+ val = read32((void *)SMAU_FLASH2_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
- writel(val, (void *)SMAU_FLASH2_TZ_BASE);
+ write32((void *)SMAU_FLASH2_TZ_BASE, val);
/* Flash 3: PNOR */
- val = readl((void *)SMAU_FLASH3_TZ_BASE);
+ val = read32((void *)SMAU_FLASH3_TZ_BASE);
val &= ~SMAU_TZ_BASE_ENABLE;
- writel(val, (void *)SMAU_FLASH3_TZ_BASE);
+ write32((void *)SMAU_FLASH3_TZ_BASE, val);
}
static void crmu_ns_config(void)
@@ -113,10 +113,10 @@
* programing the CRMU IPROC address range registers. Up to 4 access
* windows can be created
*/
- writel((CRMU_ADDR_START & CRMU_ADDR_MASK) | CRMU_ADDR_VALID,
- (void *)CRMU_IPROC_ADDR_RANGE0_LOW);
- writel((CRMU_ADDR_END & CRMU_ADDR_MASK) | CRMU_ADDR_VALID,
- (void *)CRMU_IPROC_ADDR_RANGE0_HIGH);
+ write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW,
+ (CRMU_ADDR_START & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
+ write32((void *)CRMU_IPROC_ADDR_RANGE0_HIGH,
+ (CRMU_ADDR_END & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
}
static void tz_init(void)
@@ -165,15 +165,15 @@
unsigned int val, timeout;
/* bring the DMAC block out of reset */
- val = readl((void *)DMAC_M0_IDM_RESET_CONTROL);
+ val = read32((void *)DMAC_M0_IDM_RESET_CONTROL);
val |= DMAC_RESET_MASK;
- writel(val, (void *)DMAC_M0_IDM_RESET_CONTROL);
+ write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
udelay(10);
val &= ~DMAC_RESET_MASK;
- writel(val, (void *)DMAC_M0_IDM_RESET_CONTROL);
+ write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
timeout = 0;
- while (readl((void *)DMAC_M0_IDM_RESET_CONTROL) & DMAC_RESET_MASK) {
+ while (read32((void *)DMAC_M0_IDM_RESET_CONTROL) & DMAC_RESET_MASK) {
udelay(1);
if (timeout++ > DMAC_RESET_TIMEOUT)
die("Failed to bring PL330 DMAC out of reset\n");
@@ -204,18 +204,18 @@
unsigned int i, val;
/* put Neon into reset */
- val = readl((void *)CRU_CONTROL);
+ val = read32((void *)CRU_CONTROL);
val &= ~CRU_CONTROL_NEON_RESET_N;
- writel(val, (void *)CRU_CONTROL);
+ write32((void *)CRU_CONTROL, val);
/* assert the power on register bit */
- val = readl((void *)CRU_IHOST_PWRDWN_EN);
+ val = read32((void *)CRU_IHOST_PWRDWN_EN);
val |= CRU_IHOST_PWRDWN_EN_PWRON_NEON;
- writel(val, (void *)CRU_IHOST_PWRDWN_EN);
+ write32((void *)CRU_IHOST_PWRDWN_EN, val);
/* wait for power on */
i = 0;
- while (!(readl((void *)CRU_IHOST_PWRDWN_STATUS) &
+ while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
CRU_IHOST_PWRDWN_STATUS_PWRON_NEON)) {
udelay(CRU_RETRY_INTVL_US);
if (i++ >= CRU_MAX_RETRY_COUNT)
@@ -225,13 +225,13 @@
udelay(CRU_STATUS_DELAY_US);
/* assert the power ok register bit */
- val = readl((void *)CRU_IHOST_PWRDWN_EN);
+ val = read32((void *)CRU_IHOST_PWRDWN_EN);
val |= CRU_IHOST_PWRDWN_EN_PWROK_NEON;
- writel(val, (void *)CRU_IHOST_PWRDWN_EN);
+ write32((void *)CRU_IHOST_PWRDWN_EN, val);
/* wait for power ok */
i = 0;
- while (!(readl((void *)CRU_IHOST_PWRDWN_STATUS) &
+ while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
CRU_IHOST_PWRDWN_STATUS_PWROK_NEON)) {
udelay(CRU_RETRY_INTVL_US);
if (i++ >= CRU_MAX_RETRY_COUNT)
@@ -241,16 +241,16 @@
udelay(CRU_STATUS_DELAY_US);
/* clamp off for the NEON block */
- val = readl((void *)CRU_IHOST_PWRDWN_EN);
+ val = read32((void *)CRU_IHOST_PWRDWN_EN);
val &= ~CRU_IHOST_PWRDWN_EN_CLAMPON_NEON;
- writel(val, (void *)CRU_IHOST_PWRDWN_EN);
+ write32((void *)CRU_IHOST_PWRDWN_EN, val);
udelay(CRU_STATUS_DELAY_US);
/* bring NEON out of reset */
- val = readl((void *)CRU_CONTROL);
+ val = read32((void *)CRU_CONTROL);
val |= CRU_CONTROL_NEON_RESET_N;
- writel(val, (void *)CRU_CONTROL);
+ write32((void *)CRU_CONTROL, val);
}
/*****************************************************************************
@@ -271,9 +271,9 @@
* This brings down the PCIe interfaces to the lowest possible power
* mode
*/
- val = readl((void *)CRMU_PCIE_CFG);
+ val = read32((void *)CRMU_PCIE_CFG);
val |= PCIE1_LNK_PHY_IDDQ | PCIE0_LNK_PHY_IDDQ;
- writel(val, (void *)CRMU_PCIE_CFG);
+ write32((void *)CRMU_PCIE_CFG, val);
}
/*****************************************************************************
@@ -285,7 +285,7 @@
static void M0_init(void)
{
/* Set M0 as a secure master */
- writel(CRMU_MCU_ACCESS_MODE_SECURE, (void *)CRMU_MCU_ACCESS_CONTROL);
+ write32((void *)CRMU_MCU_ACCESS_CONTROL, CRMU_MCU_ACCESS_MODE_SECURE);
}
/*****************************************************************************
@@ -405,9 +405,9 @@
uint32_t val;
uint32_t i;
for (i = 0; i < CCU_REG_TABLE_SIZE; i++) {
- val = readl((void *)(ccu_reg[i]));
+ val = read32((void *)(ccu_reg[i]));
val &= ~WR_ACCESS_PRIVATE_ACCESS_MODE;
- writel(val, (void *)(ccu_reg[i]));
+ write32((void *)(ccu_reg[i]), val);
}
}
@@ -425,9 +425,9 @@
unsigned int val;
/* make sure the LCD clock is ungated */
- val = readl((void *)ASIU_TOP_CLK_GATING_CTRL);
+ val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
val |= ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN;
- writel(val, (void *)ASIU_TOP_CLK_GATING_CTRL);
+ write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
}
/*******************************************************************
@@ -463,15 +463,15 @@
{
unsigned int val;
- val = readl((void *)AXIIC_EXT_M0_READ_QOS);
+ val = read32((void *)AXIIC_EXT_M0_READ_QOS);
val &= ~AXIIC_EXT_M0_READ_MASK;
val |= (qos & AXIIC_EXT_M0_READ_MASK);
- writel(val, (void *)AXIIC_EXT_M0_READ_QOS);
+ write32((void *)AXIIC_EXT_M0_READ_QOS, val);
- val = readl((void *)AXIIC_EXT_M0_WRITE_QOS);
+ val = read32((void *)AXIIC_EXT_M0_WRITE_QOS);
val &= ~AXIIC_EXT_M0_WRITE_MASK;
val |= (qos & AXIIC_EXT_M0_WRITE_MASK);
- writel(val, (void *)AXIIC_EXT_M0_WRITE_QOS);
+ write32((void *)AXIIC_EXT_M0_WRITE_QOS, val);
}
/*****************************************************************************
@@ -482,10 +482,10 @@
unsigned int val;
/* make sure the V3D clock is ungated */
- val = readl((void *)ASIU_TOP_CLK_GATING_CTRL);
+ val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
val |= ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN |
ASIU_TOP_CLK_GATING_CTRL_GFX_CLK_GATE_EN;
- writel(val, (void *)ASIU_TOP_CLK_GATING_CTRL);
+ write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
}
/*****************************************************************************
@@ -502,17 +502,17 @@
unsigned int val;
/* Ungate (enable) audio clock. */
- val = readl((void *)ASIU_TOP_CLK_GATING_CTRL);
+ val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
val |= ASIU_TOP_CLK_GATING_CTRL_AUD_CLK_GATE_EN;
- writel(val, (void *)ASIU_TOP_CLK_GATING_CTRL);
+ write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
/* Power on audio GEN PLL, LDO, and BG. Input isolation = normal. */
- val = readl((void *)CRMU_PLL_AON_CTRL);
+ val = read32((void *)CRMU_PLL_AON_CTRL);
val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_BG;
val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO;
val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL;
val &= ~CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN;
- writel(val, (void *)CRMU_PLL_AON_CTRL);
+ write32((void *)CRMU_PLL_AON_CTRL, val);
}
/*****************************************************************************
@@ -667,28 +667,28 @@
/*
* Disable the cmd conflict error interrupt and enable feedback clock
*/
- val = readl((void *)sdio_idm_io_control_direct_reg);
+ val = read32((void *)sdio_idm_io_control_direct_reg);
val |= SDIO_CMD_COMFLICT_DISABLE | SDIO_FEEDBACK_CLK_EN |
SDIO_CLK_ENABLE;
- writel(val, (void *)sdio_idm_io_control_direct_reg);
+ write32((void *)sdio_idm_io_control_direct_reg, val);
/*
* Set drive strength, enable hysteresis and slew rate control
*/
val = SDIO_DEFAULT_DRIVE_STRENGTH |
HYSTERESIS_ENABLE | SLEW_RATE_ENABLE;
- writel(val, (void *)cdru_sdio_io_control_reg);
+ write32((void *)cdru_sdio_io_control_reg, val);
/* Reset SDIO controller */
- val = readl((void *)sdio_idm_reset_control_reg);
+ val = read32((void *)sdio_idm_reset_control_reg);
val |= SDIO_RESET_MASK;
- writel(SDIO_RESET_MASK, (void *)sdio_idm_reset_control_reg);
+ write32((void *)sdio_idm_reset_control_reg, SDIO_RESET_MASK);
udelay(10);
val &= ~SDIO_RESET_MASK;
- writel(val, (void *)sdio_idm_reset_control_reg);
+ write32((void *)sdio_idm_reset_control_reg, val);
timeout = 0;
- while (readl((void *)sdio_idm_reset_control_reg) & SDIO_RESET_MASK) {
+ while (read32((void *)sdio_idm_reset_control_reg) & SDIO_RESET_MASK) {
udelay(1);
if (timeout++ > SDIO_RESET_TIMEOUT)
die("Failed to bring SDIO out of reset\n");
@@ -703,16 +703,16 @@
* Configure SDIO host controller capabilities
* (common setting for all SDIO controllers)
*/
- writel(SDIO_CAPS_H, (void *)CRMU_SDIO_CONTROL0);
- writel(SDIO_CAPS_L, (void *)CRMU_SDIO_CONTROL1);
+ write32((void *)CRMU_SDIO_CONTROL0, SDIO_CAPS_H);
+ write32((void *)CRMU_SDIO_CONTROL1, SDIO_CAPS_L);
/*
* Configure SDIO host controller preset values
* (common setting for all SDIO controllers)
*/
- writel(SDIO_PRESETVAL1, (void *)CRMU_SDIO_CONTROL2);
- writel(SDIO_PRESETVAL2, (void *)CRMU_SDIO_CONTROL3);
- writel(SDIO_PRESETVAL3, (void *)CRMU_SDIO_CONTROL4);
- writel(SDIO_PRESETVAL4, (void *)CRMU_SDIO_CONTROL5);
+ write32((void *)CRMU_SDIO_CONTROL2, SDIO_PRESETVAL1);
+ write32((void *)CRMU_SDIO_CONTROL3, SDIO_PRESETVAL2);
+ write32((void *)CRMU_SDIO_CONTROL4, SDIO_PRESETVAL3);
+ write32((void *)CRMU_SDIO_CONTROL5, SDIO_PRESETVAL4);
/*
* The sdhci driver attempts to change the SDIO IO voltage for UHS-I
@@ -726,9 +726,9 @@
* register to indicate success.
* (common setting for all SDIO controllers)
*/
- val = readl((void *)CRMU_SDIO_1P8_FAIL_CONTROL);
+ val = read32((void *)CRMU_SDIO_1P8_FAIL_CONTROL);
val &= ~UHS1_18V_VREG_FAIL;
- writel(val, (void *)CRMU_SDIO_1P8_FAIL_CONTROL);
+ write32((void *)CRMU_SDIO_1P8_FAIL_CONTROL, val);
/*
* Initialize each SDIO controller
diff --git a/src/soc/broadcom/cygnus/i2c.c b/src/soc/broadcom/cygnus/i2c.c
index 118120d..3d99cca 100644
--- a/src/soc/broadcom/cygnus/i2c.c
+++ b/src/soc/broadcom/cygnus/i2c.c
@@ -83,7 +83,7 @@
static unsigned int i2c_bus_busy(struct cygnus_i2c_regs *reg_addr)
{
- return readl(®_addr->i2c_master_comm) & I2C_MASTER_START_BUSY;
+ return read32(®_addr->i2c_master_comm) & I2C_MASTER_START_BUSY;
}
static int i2c_wait_bus_busy(struct cygnus_i2c_regs *reg_addr)
@@ -103,8 +103,8 @@
static void i2c_flush_fifo(struct cygnus_i2c_regs *reg_addr)
{
- writel(I2C_MASTER_RX_FIFO_FLUSH | I2C_MASTER_TX_FIFO_FLUSH,
- ®_addr->i2c_fifo_master);
+ write32(®_addr->i2c_fifo_master,
+ I2C_MASTER_RX_FIFO_FLUSH | I2C_MASTER_TX_FIFO_FLUSH);
}
static int i2c_write(struct cygnus_i2c_regs *reg_addr, struct i2c_seg *segment)
@@ -113,7 +113,7 @@
unsigned int val, status;
int i, ret;
- writel(segment->chip << 1, ®_addr->i2c_master_data_wr);
+ write32(®_addr->i2c_master_data_wr, segment->chip << 1);
for (i = 0; i < segment->len; i++) {
val = data[i];
@@ -122,16 +122,16 @@
if (i == segment->len - 1)
val |= I2C_MASTER_WR_STATUS;
- writel(val, ®_addr->i2c_master_data_wr);
+ write32(®_addr->i2c_master_data_wr, val);
}
if (segment->len == 0)
- writel(I2C_MASTER_WR_STATUS, ®_addr->i2c_master_data_wr);
+ write32(®_addr->i2c_master_data_wr, I2C_MASTER_WR_STATUS);
/*
* Now we can activate the transfer.
*/
- writel(I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_WR,
- ®_addr->i2c_master_comm);
+ write32(®_addr->i2c_master_comm,
+ I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_WR);
ret = i2c_wait_bus_busy(reg_addr);
if (ret) {
@@ -140,7 +140,7 @@
}
/* check transaction successful */
- status = readl(®_addr->i2c_master_comm);
+ status = read32(®_addr->i2c_master_comm);
ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
if (ret) {
printk(BIOS_ERR, "I2C write error %u\n", status);
@@ -160,13 +160,13 @@
int i, ret;
unsigned int status;
- writel(segment->chip << 1 | 1, ®_addr->i2c_master_data_wr);
+ write32(®_addr->i2c_master_data_wr, segment->chip << 1 | 1);
/*
* Now we can activate the transfer. Specify the number of bytes to read
*/
- writel(I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_RD | segment->len,
- ®_addr->i2c_master_comm);
+ write32(®_addr->i2c_master_comm,
+ I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_RD | segment->len);
ret = i2c_wait_bus_busy(reg_addr);
if (ret) {
@@ -175,7 +175,7 @@
}
/* check transaction successful */
- status = readl(®_addr->i2c_master_comm);
+ status = read32(®_addr->i2c_master_comm);
ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
if (ret) {
printk(BIOS_ERR, "I2C read error %u\n", status);
@@ -183,7 +183,7 @@
}
for (i = 0; i < segment->len; i++)
- data[i] = readl(®_addr->i2c_master_data_rd) &
+ data[i] = read32(®_addr->i2c_master_data_rd) &
I2C_MASTER_RD_DATA_MASK;
return 0;
@@ -259,10 +259,10 @@
i2c_flush_fifo(regs);
/* disable all interrupts */
- writel(0, ®s->i2c_int_en);
+ write32(®s->i2c_int_en, 0);
/* clear all pending interrupts */
- writel(0xffffffff, ®s->i2c_int_status);
+ write32(®s->i2c_int_status, 0xffffffff);
- writel(I2C_SMB_EN, ®s->i2c_con);
+ write32(®s->i2c_con, I2C_SMB_EN);
}
diff --git a/src/soc/broadcom/cygnus/iomux.c b/src/soc/broadcom/cygnus/iomux.c
index 1be5c36..f684def 100644
--- a/src/soc/broadcom/cygnus/iomux.c
+++ b/src/soc/broadcom/cygnus/iomux.c
@@ -269,9 +269,9 @@
if (!mux->is_supported)
return -ENOTSUPP;
- val = readl(pinctrl->base1 + mux->offset);
+ val = read32(pinctrl->base1 + mux->offset);
val |= 0x3 << mux->shift;
- writel(val, pinctrl->base1 + mux->offset);
+ write32(pinctrl->base1 + mux->offset, val);
printk(BIOS_INFO, "gpio request enable pin=%u offset=0x%x shift=%u\n",
pin, mux->offset, mux->shift);
@@ -288,9 +288,9 @@
if (!mux->is_supported)
return;
- val = readl(pinctrl->base1 + mux->offset);
+ val = read32(pinctrl->base1 + mux->offset);
val &= ~(0x3 << mux->shift);
- writel(val, pinctrl->base1 + mux->offset);
+ write32(pinctrl->base1 + mux->offset, val);
printk(BIOS_INFO, "gpio disable free pin=%u offset=0x%x shift=%u\n",
pin, mux->offset, mux->shift);
diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c
index be3e8d0..8e58d47 100644
--- a/src/soc/broadcom/cygnus/spi.c
+++ b/src/soc/broadcom/cygnus/spi.c
@@ -73,8 +73,8 @@
/*
* Register access macros
*/
-#define REG_RD(x) readl(x)
-#define REG_WR(x, y) writel((y), (x))
+#define REG_RD(x) read32(x)
+#define REG_WR(x, y) write32((x), (y))
#define REG_CLR(x, y) REG_WR((x), REG_RD(x) & ~(y))
#define REG_SET(x, y) REG_WR((x), REG_RD(x) | (y))
diff --git a/src/soc/broadcom/cygnus/tz.c b/src/soc/broadcom/cygnus/tz.c
index 95367a2..e35669b 100644
--- a/src/soc/broadcom/cygnus/tz.c
+++ b/src/soc/broadcom/cygnus/tz.c
@@ -95,25 +95,25 @@
if (masters & TZPCDECPROT0_MASK) {
val = masters & TZPCDECPROT0_MASK;
if (ns_bit)
- writel(val, (void *)TZPC_TZPCDECPROT0SET);
+ write32((void *)TZPC_TZPCDECPROT0SET, val);
else
- writel(val, (void *)TZPC_TZPCDECPROT0CLR);
+ write32((void *)TZPC_TZPCDECPROT0CLR, val);
}
/* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */
if ((masters >> 8) & TZPCDECPROT1_MASK) {
val = (masters >> 8) & TZPCDECPROT1_MASK;
if (ns_bit)
- writel(val, (void *)TZPC_TZPCDECPROT1SET);
+ write32((void *)TZPC_TZPCDECPROT1SET, val);
else
- writel(val, (void *)TZPC_TZPCDECPROT1CLR);
+ write32((void *)TZPC_TZPCDECPROT1CLR, val);
}
/* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */
if ((masters >> 16) & TZPCDECPROT2_MASK) {
val = (masters >> 16) & TZPCDECPROT2_MASK;
if (ns_bit)
- writel(val, (void *)TZPC_TZPCDECPROT2SET);
+ write32((void *)TZPC_TZPCDECPROT2SET, val);
else
- writel(val, (void *)TZPC_TZPCDECPROT2CLR);
+ write32((void *)TZPC_TZPCDECPROT2CLR, val);
}
}
@@ -132,7 +132,7 @@
slave_vector = slave_vector & mask;
for (i = 0; i < total; i++) {
if (slave_vector & (0x1 << i))
- writel(ns_bit, (void *)(non_virtual_slave_regs[i]));
+ write32((void *)(non_virtual_slave_regs[i]), ns_bit);
}
}
@@ -146,8 +146,8 @@
uint32_t mask_x = AXIIC_APBX_s0_security_MASK;
uint32_t mask_y = AXIIC_APBY_s0_security_MASK;
uint32_t tz_periphs_sec_status =
- (mask_x & readl((void *)AXIIC_APBX_s0_security)) |
- ((mask_y & readl((void *)AXIIC_APBY_s0_security)) << 16);
+ (mask_x & read32((void *)AXIIC_APBX_s0_security)) |
+ ((mask_y & read32((void *)AXIIC_APBY_s0_security)) << 16);
if (ns_bit == TZ_STATE_SECURE)
tz_periphs_sec_status &= ~slave_vector;
@@ -155,10 +155,10 @@
tz_periphs_sec_status |= slave_vector;
val = tz_periphs_sec_status & mask_x;
- writel(val, (void *)AXIIC_APBX_s0_security);
+ write32((void *)AXIIC_APBX_s0_security, val);
val = (tz_periphs_sec_status >> 16) & mask_y;
- writel(val, (void *)AXIIC_APBY_s0_security);
+ write32((void *)AXIIC_APBY_s0_security, val);
}
/*
@@ -170,7 +170,7 @@
uint32_t val;
uint32_t mask = AXIIC_APBZ_s0_security_MASK;
uint32_t tz_sec_periphs_sec_status =
- readl((void *)AXIIC_APBZ_s0_security);
+ read32((void *)AXIIC_APBZ_s0_security);
if (ns_bit == TZ_STATE_SECURE)
tz_sec_periphs_sec_status &= ~slave_vector;
@@ -178,7 +178,7 @@
tz_sec_periphs_sec_status |= slave_vector;
val = tz_sec_periphs_sec_status & mask;
- writel(val, (void *)AXIIC_APBZ_s0_security);
+ write32((void *)AXIIC_APBZ_s0_security, val);
}
/*
@@ -191,8 +191,8 @@
uint32_t mask_s0 = AXIIC_ext_s0_security_MASK;
uint32_t mask_s1 = AXIIC_ext_s1_security_MASK;
uint32_t tz_ext_slaves_sec_status =
- (mask_s0 & readl((void *)AXIIC_ext_s0_security)) |
- ((mask_s1 & readl((void *)AXIIC_ext_s0_security)) << 16);
+ (mask_s0 & read32((void *)AXIIC_ext_s0_security)) |
+ ((mask_s1 & read32((void *)AXIIC_ext_s0_security)) << 16);
if (ns_bit == TZ_STATE_SECURE)
tz_ext_slaves_sec_status &= ~slave_vector;
@@ -200,10 +200,10 @@
tz_ext_slaves_sec_status |= slave_vector;
val = tz_ext_slaves_sec_status & mask_s0;
- writel(val, (void *)AXIIC_ext_s0_security);
+ write32((void *)AXIIC_ext_s0_security, val);
val = (tz_ext_slaves_sec_status >> 16) & mask_s1;
- writel(val, (void *)AXIIC_ext_s1_security);
+ write32((void *)AXIIC_ext_s1_security, val);
}
/*
@@ -216,8 +216,8 @@
uint32_t mask_r = AXIIC_APBR_s0_security_MASK;
uint32_t mask_s = AXIIC_APBS_s0_security_MASK;
uint32_t tz_cfg_slaves_sec_status =
- (mask_r & readl((void *)AXIIC_APBR_s0_security)) |
- ((mask_s & readl((void *)AXIIC_APBS_s0_security)) << 16);
+ (mask_r & read32((void *)AXIIC_APBR_s0_security)) |
+ ((mask_s & read32((void *)AXIIC_APBS_s0_security)) << 16);
if (ns_bit == TZ_STATE_SECURE)
tz_cfg_slaves_sec_status &= ~slave_vector;
@@ -225,10 +225,10 @@
tz_cfg_slaves_sec_status |= slave_vector;
val = tz_cfg_slaves_sec_status & mask_r;
- writel(val, (void *)AXIIC_APBR_s0_security);
+ write32((void *)AXIIC_APBR_s0_security, val);
val = (tz_cfg_slaves_sec_status >> 16) & mask_s;
- writel(val, (void *)AXIIC_APBS_s0_security);
+ write32((void *)AXIIC_APBS_s0_security, val);
}
/*
@@ -245,7 +245,7 @@
{
uint32_t mask = TZPC_TZPCR0SIZE_MASK;
- writel(r0size & mask, (void *)TZPC_TZPCR0SIZE);
+ write32((void *)TZPC_TZPCR0SIZE, r0size & mask);
}
/*
@@ -260,10 +260,10 @@
uint32_t mask_w3 = AXIIC_APB_W3_security_MASK;
uint32_t mask_w2 = AXIIC_APB_W2_security_MASK;
uint32_t mask_w1 = AXIIC_APB_W1_security_MASK;
- uint32_t tz_wrapper1_sec_status = readl((void *)AXIIC_APB_W1_security);
- uint32_t tz_wrapper2_sec_status = readl((void *)AXIIC_APB_W2_security);
- uint32_t tz_wrapper3_sec_status = readl((void *)AXIIC_APB_W3_security);
- uint32_t tz_wrapper4_sec_status = readl((void *)AXIIC_APB_W4_security);
+ uint32_t tz_wrapper1_sec_status = read32((void *)AXIIC_APB_W1_security);
+ uint32_t tz_wrapper2_sec_status = read32((void *)AXIIC_APB_W2_security);
+ uint32_t tz_wrapper3_sec_status = read32((void *)AXIIC_APB_W3_security);
+ uint32_t tz_wrapper4_sec_status = read32((void *)AXIIC_APB_W4_security);
if (ns_bit == TZ_STATE_SECURE) {
tz_wrapper1_sec_status &= ~wrapper1;
@@ -276,12 +276,12 @@
tz_wrapper3_sec_status |= wrapper3;
tz_wrapper4_sec_status |= wrapper4;
}
- writel(tz_wrapper1_sec_status & mask_w1,
- (void *)AXIIC_APB_W1_security);
- writel(tz_wrapper2_sec_status & mask_w2,
- (void *)AXIIC_APB_W2_security);
- writel(tz_wrapper3_sec_status & mask_w3,
- (void *)AXIIC_APB_W3_security);
- writel(tz_wrapper4_sec_status & mask_w4,
- (void *)AXIIC_APB_W4_security);
+ write32((void *)AXIIC_APB_W1_security,
+ tz_wrapper1_sec_status & mask_w1);
+ write32((void *)AXIIC_APB_W2_security,
+ tz_wrapper2_sec_status & mask_w2);
+ write32((void *)AXIIC_APB_W3_security,
+ tz_wrapper3_sec_status & mask_w3);
+ write32((void *)AXIIC_APB_W4_security,
+ tz_wrapper4_sec_status & mask_w4);
}
diff --git a/src/soc/broadcom/cygnus/usb.c b/src/soc/broadcom/cygnus/usb.c
index 557f1cb..af140ab 100644
--- a/src/soc/broadcom/cygnus/usb.c
+++ b/src/soc/broadcom/cygnus/usb.c
@@ -68,9 +68,9 @@
* Default setting is device, check if it is set to host */
if (instance_ptr->port == 2) {
if (instance_ptr->host_mode == PHY2_DEV_HOST_CTRL_SEL_HOST)
- writel(PHY2_DEV_HOST_CTRL_SEL_HOST,
- phy_driver.usbphy_regs +
- CDRU_USBPHY2_HOST_DEV_SEL_OFFSET);
+ write32(phy_driver.usbphy_regs +
+ CDRU_USBPHY2_HOST_DEV_SEL_OFFSET,
+ PHY2_DEV_HOST_CTRL_SEL_HOST);
else
die("usb device mode unsupported\n");
}
@@ -84,14 +84,14 @@
u32 val;
/* Bring the AFE block out of reset to start powering up the PHY */
- val = readl(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET);
+ val = read32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET);
if (instance_ptr->port == 0)
val |= (1 << CRMU_USBPHY_P0_AFE_CORERDY_VDDC);
else if (instance_ptr->port == 1)
val |= (1 << CRMU_USBPHY_P1_AFE_CORERDY_VDDC);
else if (instance_ptr->port == 2)
val |= (1 << CRMU_USBPHY_P2_AFE_CORERDY_VDDC);
- writel(val, phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET);
+ write32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET, val);
instance_ptr->power = 1;
@@ -100,7 +100,7 @@
instance_ptr->host_mode == PHY2_DEV_HOST_CTRL_SEL_DEVICE)
die("usb device mode unsupported\n");
- val = readl(phy_driver.usbphy_regs + CDRU_USBPHY_CLK_RST_SEL_OFFSET);
+ val = read32(phy_driver.usbphy_regs + CDRU_USBPHY_CLK_RST_SEL_OFFSET);
/* Check if the phy that is configured
* to provide clock and reset is powered on*/
@@ -112,8 +112,8 @@
/* if not set the current phy */
if (clock_reset_flag) {
val = instance_ptr->port;
- writel(val, phy_driver.usbphy_regs +
- CDRU_USBPHY_CLK_RST_SEL_OFFSET);
+ write32(phy_driver.usbphy_regs + CDRU_USBPHY_CLK_RST_SEL_OFFSET,
+ val);
}
if (phy_driver.idm_host_enabled != 1) {
