braswell: remove unneeded gfx init from romstage given fsp usage
BRANCH=none
BUG=none
TEST=Build and boot on Cyan
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Change-Id: I8ea5676ab27370c23e8445c9c56381299158a2b6
Reviewed-on: https://chromium-review.googlesource.com/267475
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Tested-by: Robbie Zhang <robbie.zhang@intel.com>
diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc
index 7d7271d..89c0083 100644
--- a/src/soc/intel/braswell/romstage/Makefile.inc
+++ b/src/soc/intel/braswell/romstage/Makefile.inc
@@ -1,7 +1,6 @@
cpu_incs-y += $(src)/drivers/intel/fsp/fsp_1_1.inc
romstage-y += early_spi.c
-romstage-y += gfx.c
romstage-y += pmc.c
romstage-y += romstage.c
diff --git a/src/soc/intel/braswell/romstage/gfx.c b/src/soc/intel/braswell/romstage/gfx.c
deleted file mode 100644
index e7b0ad3..0000000
--- a/src/soc/intel/braswell/romstage/gfx.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <soc/gfx.h>
-#include <soc/pci_devs.h>
-#include <soc/romstage.h>
-
-void gfx_init(void)
-{
- uint32_t ggc;
- uint8_t msac;
- const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC);
-
- /*
- * The GFX device needs to set the aperture, gtt stolen size, and
- * graphics stolen memory stolen size before running MRC. For now
- * just hard code the defaults. Options can be added to the device
- * tree if needed.
- */
-
- ggc = pci_read_config32(gfx_dev, GGC);
- msac = pci_read_config8(gfx_dev, MSAC);
-
- ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK);
- /* 32MB GSM is not supported with <C0 stepping. */
- ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB;
- /* Enable VGA decoding as well. */
- ggc &= ~(GGC_VGA_DISABLE);
-
- msac &= ~(APERTURE_SIZE_MASK);
- msac |= APERTURE_SIZE_256MB;
-
- pci_write_config32(gfx_dev, GGC, ggc);
- pci_write_config8(gfx_dev, MSAC, msac);
-}
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 0e75fcd..9a5f1b9 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -39,7 +39,6 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <fsp_util.h>
#include <soc/intel/common/mrc_cache.h>
-
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
@@ -187,7 +186,6 @@
{
/* Continue chipset initialization */
spi_init();
- gfx_init();
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* Ensure the EC is in the right mode for recovery */
