Strago: Support common code
Update the strago code to use the common romstage.c code. The PEI_DATA
structure is passed in as a pointer in romstage_params. Use the common
UART initialization routine name.
BRANCH=none
BUG=None
TEST=Build and run on strago
Test is successful if post code is 0x35.
Post code of 0x37 indicates that the FSP binary is broken, not properly
returning the necessary HOBs! Workaround is to disable
CONFIG_DISPLAY_HOBS in config.strago.
Change-Id: Ibcc532dd7a4f57520a104ea089364ee33394e65c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/261393
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c
index e8f7902..5a18b63 100644
--- a/src/mainboard/intel/strago/com_init.c
+++ b/src/mainboard/intel/strago/com_init.c
@@ -54,7 +54,7 @@
return (i << 8) + pad - base;
}
-void config_com1_and_enable(void)
+void mainboard_pre_console_init(struct romstage_params *params)
{
uint32_t reg;
uint16_t fpad;
diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c
index 31d3932..04f9a4e 100644
--- a/src/mainboard/intel/strago/romstage.c
+++ b/src/mainboard/intel/strago/romstage.c
@@ -59,7 +59,7 @@
struct cbfs_file *spd_file;
void *spd_content;
int dual_channel = 0;
- struct pei_data ps;
+ struct pei_data *ps = rp->pei_data;
/* Find the SPD data in CBFS. */
spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin");
@@ -79,9 +79,6 @@
printk(BIOS_DEBUG, "\n");
}
- /* Initialize the pei data structure */
- memset(&ps, 0, sizeof(ps));
-
/*
* Set SPD and memory configuration:
* Memory type: 0=DimmInstalled,
@@ -89,17 +86,16 @@
* 2=DimmDisabled
*/
if (spd_content != NULL) {
- ps.spd_data_ch0 = spd_content;
- ps.spd_ch0_config = 1;
- ps.spd_ch1_config = 2;
+ ps->spd_data_ch0 = spd_content;
+ ps->spd_ch0_config = 1;
+ ps->spd_ch1_config = 2;
}
/* Set device state/enable information */
- ps.sdcard_mode = PCH_ACPI_MODE;
- ps.emmc_mode = PCH_ACPI_MODE;
- ps.enable_azalia = 1;
+ ps->sdcard_mode = PCH_ACPI_MODE;
+ ps->emmc_mode = PCH_ACPI_MODE;
+ ps->enable_azalia = 1;
/* Call back into chipset code with platform values updated. */
- rp->pei_data = &ps;
romstage_common(rp);
}
