commit 47b86e2893fa667bebada6a0e0b443886dd5ee02
author Vince Hsu <vinceh@nvidia.com> Fri May 16 18:07:53 2014 +0800
committer chrome-internal-fetch <chrome-internal-fetch@google.com> Wed May 21 04:16:35 2014 +0000
tree f0c38bea44fb2dc52cb6b44b9adef4b70e2a5614
parent dc3cc253c319c21772c30962d963ec9dfc4944a7

tegra124: Active dc/sor register change immediately

When doing DP attach, we need to make sure the register change to
take effect immediately, otherwise it may fail to catch the attach
timing.

BRANCH=None
BUG=chrome-os-partner:28128
TEST=Display works and system boots up on Nyan and Big

Change-Id: I569dc435a1aa4aac0d5ecd0655d2ad87a791246d
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/200414
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>

src/soc/nvidia/tegra124/sor.c

diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c
index cf22199..2f18f8b 100644
--- a/src/soc/nvidia/tegra124/sor.c
+++ b/src/soc/nvidia/tegra124/sor.c
@@ -763,9 +763,11 @@
 	tegra_dc_sor_super_update(sor);
 
 	/* Enable dc */
+	reg_val = READL(&disp_ctrl->cmd.state_access);
+	WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
 	WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
 	WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
-	WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
+	WRITEL(reg_val, &disp_ctrl->cmd.state_access);
 
 	if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
 			NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,