| # SPDX-License-Identifier: GPL-2.0-only |
| |
| config SOC_AMD_PICASSO |
| bool |
| help |
| AMD Picasso support |
| |
| if SOC_AMD_PICASSO |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select ARCH_X86 |
| select RESET_VECTOR_IN_RAM |
| select X86_AMD_FIXED_MTRRS |
| select X86_INIT_NEED_1_SIPI |
| select ACPI_SOC_NVS |
| select ADD_FSP_BINARIES if USE_AMD_BLOBS |
| select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| select DRIVERS_I2C_DESIGNWARE |
| select DRIVERS_USB_PCI_XHCI |
| select GENERIC_GPIO_LIB |
| select IDT_IN_EVERY_STAGE |
| select HAVE_ACPI_TABLES |
| select HAVE_EM100_SUPPORT |
| select SOC_AMD_COMMON |
| select SOC_AMD_COMMON_BLOCK_ACP |
| select SOC_AMD_COMMON_BLOCK_ACPI |
| select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| select SOC_AMD_COMMON_BLOCK_ACPI_ALIB |
| select SOC_AMD_COMMON_BLOCK_ACPI_GPIO |
| select SOC_AMD_COMMON_BLOCK_ACPI_IVRS |
| select SOC_AMD_COMMON_BLOCK_AOAC |
| select SOC_AMD_COMMON_BLOCK_APOB |
| select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| select SOC_AMD_COMMON_BLOCK_DATA_FABRIC |
| select SOC_AMD_COMMON_BLOCK_GRAPHICS |
| select SOC_AMD_COMMON_BLOCK_HAS_ESPI |
| select SOC_AMD_COMMON_BLOCK_HDA |
| select SOC_AMD_COMMON_BLOCK_I2C |
| select SOC_AMD_COMMON_BLOCK_IOMMU |
| select SOC_AMD_COMMON_BLOCK_LPC |
| select SOC_AMD_COMMON_BLOCK_MCAX |
| select SOC_AMD_COMMON_BLOCK_NONCAR |
| select SOC_AMD_COMMON_BLOCK_PCI |
| select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER |
| select SOC_AMD_COMMON_BLOCK_PM |
| select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE |
| select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
| select SOC_AMD_COMMON_BLOCK_SATA |
| select SOC_AMD_COMMON_BLOCK_SMBUS |
| select SOC_AMD_COMMON_BLOCK_SMI |
| select SOC_AMD_COMMON_BLOCK_SMM |
| select SOC_AMD_COMMON_BLOCK_SMU |
| select SOC_AMD_COMMON_BLOCK_SPI |
| select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H |
| select SOC_AMD_COMMON_BLOCK_UART |
| select SOC_AMD_COMMON_BLOCK_UCODE |
| select SOC_AMD_COMMON_FSP_DMI_TABLES |
| select PROVIDES_ROM_SHARING |
| select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| select PARALLEL_MP_AP_WORK |
| select HAVE_SMI_HANDLER |
| select SSE2 |
| select RTC |
| select PLATFORM_USES_FSP2_0 |
| select FSP_COMPRESS_FSP_M_LZMA |
| select FSP_COMPRESS_FSP_S_LZMA |
| select UDK_2017_BINDING |
| select HAVE_CF9_RESET |
| |
| config ARCH_ALL_STAGES_X86 |
| default n |
| |
| config SOC_AMD_COMMON_BLOCK_UCODE_SIZE |
| default 3200 |
| |
| config CHIPSET_DEVICETREE |
| string |
| default "soc/amd/picasso/chipset.cb" |
| |
| config FSP_M_FILE |
| string "FSP-M (memory init) binary path and filename" |
| depends on ADD_FSP_BINARIES |
| default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" |
| help |
| The path and filename of the FSP-M binary for this platform. |
| |
| config FSP_S_FILE |
| string "FSP-S (silicon init) binary path and filename" |
| depends on ADD_FSP_BINARIES |
| default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" |
| help |
| The path and filename of the FSP-S binary for this platform. |
| |
| config EARLY_RESERVED_DRAM_BASE |
| hex |
| default 0x2000000 |
| help |
| This variable defines the base address of the DRAM which is reserved |
| for usage by coreboot in early stages (i.e. before ramstage is up). |
| This memory gets reserved in BIOS tables to ensure that the OS does |
| not use it, thus preventing corruption of OS memory in case of S3 |
| resume. |
| |
| config EARLYRAM_BSP_STACK_SIZE |
| hex |
| default 0x1000 |
| |
| config PSP_APOB_DRAM_ADDRESS |
| hex |
| default 0x2001000 |
| help |
| Location in DRAM where the PSP will copy the AGESA PSP Output |
| Block. |
| |
| config PSP_SHAREDMEM_BASE |
| hex |
| default 0x2011000 if VBOOT |
| default 0x0 |
| help |
| This variable defines the base address in DRAM memory where PSP copies |
| the vboot workbuf. This is used in the linker script to have a static |
| allocation for the buffer as well as for adding relevant entries in |
| the BIOS directory table for the PSP. |
| |
| config PSP_SHAREDMEM_SIZE |
| hex |
| default 0x8000 if VBOOT |
| default 0x0 |
| help |
| Sets the maximum size for the PSP to pass the vboot workbuf and |
| any logs or timestamps back to coreboot. This will be copied |
| into main memory by the PSP and will be available when the x86 is |
| started. The workbuf's base depends on the address of the reset |
| vector. |
| |
| config PRERAM_CBMEM_CONSOLE_SIZE |
| hex |
| default 0x1600 |
| help |
| Increase this value if preram cbmem console is getting truncated |
| |
| config CBFS_MCACHE_SIZE |
| hex |
| default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK |
| |
| config C_ENV_BOOTBLOCK_SIZE |
| hex |
| default 0x10000 |
| help |
| Sets the size of the bootblock stage that should be loaded in DRAM. |
| This variable controls the DRAM allocation size in linker script |
| for bootblock stage. |
| |
| config ROMSTAGE_ADDR |
| hex |
| default 0x2040000 |
| help |
| Sets the address in DRAM where romstage should be loaded. |
| |
| config ROMSTAGE_SIZE |
| hex |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for romstage in linker script. |
| |
| config FSP_M_ADDR |
| hex |
| default 0x20C0000 |
| help |
| Sets the address in DRAM where FSP-M should be loaded. cbfstool |
| performs relocation of FSP-M to this address. |
| |
| config FSP_M_SIZE |
| hex |
| default 0xC0000 |
| help |
| Sets the size of DRAM allocation for FSP-M in linker script. |
| |
| config VERSTAGE_ADDR |
| hex |
| depends on VBOOT_SEPARATE_VERSTAGE |
| default 0x2180000 |
| help |
| Sets the address in DRAM where verstage should be loaded if running |
| as a separate stage on x86. |
| |
| config VERSTAGE_SIZE |
| hex |
| depends on VBOOT_SEPARATE_VERSTAGE |
| default 0x80000 |
| help |
| Sets the size of DRAM allocation for verstage in linker script if |
| running as a separate stage on x86. |
| |
| config RAMBASE |
| hex |
| default 0x10000000 |
| |
| config ECAM_MMCONF_BASE_ADDRESS |
| default 0xF8000000 |
| |
| config ECAM_MMCONF_BUS_NUMBER |
| default 64 |
| |
| config VERSTAGE_ADDR |
| hex |
| default 0x4000000 |
| |
| config MAX_CPUS |
| int |
| default 8 |
| help |
| Maximum number of threads the platform can have. |
| |
| config VGA_BIOS_ID |
| string |
| default "1002,15d8,c1" |
| help |
| The default VGA BIOS PCI vendor/device ID should be set to the |
| result of the map_oprom_vendev_rev() function in northbridge.c. |
| |
| config VGA_BIOS_FILE |
| string |
| default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" |
| |
| config VGA_BIOS_SECOND |
| def_bool y |
| |
| config VGA_BIOS_SECOND_ID |
| string |
| default "1002,15dd,c4" |
| help |
| Because Dali and Picasso need different video BIOSes, but have the |
| same vendor/device IDs, we need an alternate method to determine the |
| correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid |
| and decide which rom to load. |
| |
| Even though the hardware has the same vendor/device IDs, the vBIOS |
| contains a *different* device ID, confusing the situation even more. |
| |
| config VGA_BIOS_SECOND_FILE |
| string |
| default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" |
| |
| config CHECK_REV_IN_OPROM_NAME |
| bool |
| default y |
| help |
| Select this in the platform BIOS or chipset if the option rom has a |
| revision that needs to be checked when searching CBFS. |
| |
| config S3_VGA_ROM_RUN |
| bool |
| default n |
| |
| config HEAP_SIZE |
| hex |
| default 0xc0000 |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default n |
| help |
| Set this option to y for serial IRQ in continuous mode. |
| Otherwise it is in quiet mode. |
| |
| config CONSOLE_UART_BASE_ADDRESS |
| depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART |
| hex |
| default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| default 0xfedce000 if UART_FOR_CONSOLE = 2 |
| default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 if HAVE_SMI_HANDLER |
| default 0x0 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x180000 |
| |
| config SMM_MODULE_STACK_SIZE |
| hex |
| default 0x800 |
| |
| config ACPI_CPU_STRING |
| string |
| default "\\_SB.C%03d" |
| |
| config ACPI_BERT |
| bool "Build ACPI BERT Table" |
| default y |
| depends on HAVE_ACPI_TABLES |
| help |
| Report Machine Check errors identified in POST to the OS in an |
| ACPI Boot Error Record Table. |
| |
| config ACPI_BERT_SIZE |
| hex |
| default 0x4000 if ACPI_BERT |
| default 0x0 |
| help |
| Specify the amount of DRAM reserved for gathering the data used to |
| generate the ACPI table. |
| |
| config ACPI_SSDT_PSD_INDEPENDENT |
| bool "Allow core p-state independent transitions" |
| default y |
| help |
| AMD recommends the ACPI _PSD object to be configured to cause |
| cores to transition between p-states independently. A vendor may |
| choose to generate _PSD object to allow cores to transition together. |
| |
| config CHROMEOS |
| select ALWAYS_LOAD_OPROM |
| select ALWAYS_RUN_OPROM |
| |
| config RO_REGION_ONLY |
| string |
| depends on CHROMEOS |
| default "apu/amdfw" |
| |
| config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| int |
| default 150 |
| |
| config DISABLE_SPI_FLASH_ROM_SHARING |
| def_bool n |
| help |
| Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin |
| which indicates a board level ROM transaction request. This |
| removes arbitration with board and assumes the chipset controls |
| the SPI flash bus entirely. |
| |
| config DISABLE_KEYBOARD_RESET_PIN |
| bool |
| help |
| Instruct the SoC to not use the state of GPIO_129 as keyboard reset |
| signal. When this pin is used as GPIO and the keyboard reset |
| functionality isn't disabled, configuring it as an output and driving |
| it as 0 will cause a reset. |
| |
| config FSP_TEMP_RAM_SIZE |
| hex |
| default 0x40000 |
| help |
| The amount of coreboot-allocated heap and stack usage by the FSP. |
| |
| menu "PSP Configuration Options" |
| |
| config AMD_FWM_POSITION_INDEX |
| int "Firmware Directory Table location (0 to 5)" |
| range 0 5 |
| default 0 if BOARD_ROMSIZE_KB_512 |
| default 1 if BOARD_ROMSIZE_KB_1024 |
| default 2 if BOARD_ROMSIZE_KB_2048 |
| default 3 if BOARD_ROMSIZE_KB_4096 |
| default 4 if BOARD_ROMSIZE_KB_8192 |
| default 5 if BOARD_ROMSIZE_KB_16384 |
| help |
| Typically this is calculated by the ROM size, but there may |
| be situations where you want to put the firmware directory |
| table in a different location. |
| 0: 512 KB - 0xFFFA0000 |
| 1: 1 MB - 0xFFF20000 |
| 2: 2 MB - 0xFFE20000 |
| 3: 4 MB - 0xFFC20000 |
| 4: 8 MB - 0xFF820000 |
| 5: 16 MB - 0xFF020000 |
| |
| comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 0 |
| comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 1 |
| comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 2 |
| comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 3 |
| comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 4 |
| comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| depends on AMD_FWM_POSITION_INDEX = 5 |
| |
| config AMDFW_CONFIG_FILE |
| string |
| default "src/soc/amd/picasso/fw.cfg" |
| |
| config PSP_LOAD_MP2_FW |
| bool |
| default n |
| help |
| Include the MP2 firmwares and configuration into the PSP build. |
| |
| If unsure, answer 'n' |
| |
| config PSP_LOAD_S0I3_FW |
| bool |
| default n |
| help |
| Select this item to include the S0i3 file into the PSP build. |
| |
| config HAVE_PSP_WHITELIST_FILE |
| bool "Include a debug whitelist file in PSP build" |
| default n |
| help |
| Support secured unlock prior to reset using a whitelisted |
| number? This feature requires a signed whitelist image and |
| bootloader from AMD. |
| |
| If unsure, answer 'n' |
| |
| config PSP_WHITELIST_FILE |
| string "Debug whitelist file path" |
| depends on HAVE_PSP_WHITELIST_FILE |
| default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" |
| |
| config PSP_UNLOCK_SECURE_DEBUG |
| bool "Unlock secure debug" |
| default n |
| help |
| Select this item to enable secure debug options in PSP. |
| |
| config PSP_VERSTAGE_FILE |
| string "Specify the PSP_verstage file path" |
| depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| default "\$(obj)/psp_verstage.bin" |
| help |
| Add psp_verstage file to the build & PSP Directory Table |
| |
| config PSP_VERSTAGE_SIGNING_TOKEN |
| string "Specify the PSP_verstage Signature Token file path" |
| depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| default "" |
| help |
| Add psp_verstage signature token to the build & PSP Directory Table |
| |
| config PSP_SOFTFUSE_BITS |
| string "PSP Soft Fuse bits to enable" |
| default "28" |
| help |
| Space separated list of Soft Fuse bits to enable. |
| Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) |
| Bit 15: PSP post code destination: 0=LPC 1=eSPI |
| Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) |
| |
| See #55758 (NDA) for additional bit definitions. |
| |
| endmenu |
| |
| config VBOOT |
| select VBOOT_VBNV_CMOS |
| select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| |
| config VBOOT_STARTS_BEFORE_BOOTBLOCK |
| def_bool n |
| depends on VBOOT |
| select ARCH_VERSTAGE_ARMV7 |
| help |
| Runs verstage on the PSP. Only available on |
| certain Chrome OS branded parts from AMD. |
| |
| config VBOOT_HASH_BLOCK_SIZE |
| hex |
| default 0x9000 |
| depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| help |
| Because the bulk of the time in psp_verstage to hash the RO cbfs is |
| spent in the overhead of doing svc calls, increasing the hash block |
| size significantly cuts the verstage hashing time as seen below. |
| |
| 4k takes 180ms |
| 16k takes 44ms |
| 32k takes 33.7ms |
| 36k takes 32.5ms |
| There's actually still room for an even bigger stack, but we've |
| reached a point of diminishing returns. |
| |
| config CMOS_RECOVERY_BYTE |
| hex |
| default 0x51 |
| depends on VBOOT_STARTS_BEFORE_BOOTBLOCK |
| help |
| If the workbuf is not passed from the PSP to coreboot, set the |
| recovery flag and reboot. The PSP will read this byte, mark the |
| recovery request in VBNV, and reset the system into recovery mode. |
| |
| This is the byte before the default first byte used by VBNV |
| (0x26 + 0x0E - 1) |
| |
| if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| |
| config RWA_REGION_ONLY |
| string |
| default "apu/amdfw_a" |
| help |
| Add a space-delimited list of filenames that should only be in the |
| RW-A section. |
| |
| config RWB_REGION_ONLY |
| string |
| default "apu/amdfw_b" |
| help |
| Add a space-delimited list of filenames that should only be in the |
| RW-B section. |
| |
| config PICASSO_FW_A_POSITION |
| hex |
| help |
| Location of the AMD firmware in the RW_A region |
| |
| config PICASSO_FW_B_POSITION |
| hex |
| help |
| Location of the AMD firmware in the RW_B region |
| |
| endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK |
| |
| endif # SOC_AMD_PICASSO |
